//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_3d_wrapper.v
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// fm_3d_wrapper.v
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//
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//
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// Abstract:
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// Abstract:
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// Monophony core top module AVALON version
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// Monophony core top module AVALON version
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_avalon(
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module fm_avalon(
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// AVALON bus
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// AVALON bus
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i_av_adr,
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i_av_adr,
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i_av_be,
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i_av_be,
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i_av_r,
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i_av_r,
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o_av_rd,
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o_av_rd,
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i_av_w,
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i_av_w,
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i_av_wd,
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i_av_wd,
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o_av_wait,
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o_av_wait,
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// internal side
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// internal side
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o_req,
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o_req,
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o_wr,
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o_wr,
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o_adrs,
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o_adrs,
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i_ack,
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i_ack,
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o_be,
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o_be,
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o_wd,
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o_wd,
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i_rstr,
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i_rstr,
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i_rd
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i_rd
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);
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);
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parameter P_AVALON_ADR_WIDTH='d10;
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parameter P_AVALON_ADR_WIDTH='d10;
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parameter P_AVALON_BE_WIDTH='d4;
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parameter P_AVALON_BE_WIDTH='d4;
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parameter P_AVALON_DATA_WIDTH='d32;
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parameter P_AVALON_DATA_WIDTH='d32;
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parameter P_INTERNAL_ADR_WIDTH=P_AVALON_ADR_WIDTH;
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parameter P_INTERNAL_ADR_WIDTH=P_AVALON_ADR_WIDTH;
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parameter P_INTERNAL_BE_WIDTH=P_AVALON_BE_WIDTH;
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parameter P_INTERNAL_BE_WIDTH=P_AVALON_BE_WIDTH;
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parameter P_INTERNAL_DATA_WIDTH=P_AVALON_DATA_WIDTH;
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parameter P_INTERNAL_DATA_WIDTH=P_AVALON_DATA_WIDTH;
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// AVALON Bus
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// AVALON Bus
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input [P_AVALON_ADR_WIDTH-1:0]
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input [P_AVALON_ADR_WIDTH-1:0]
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i_av_adr;
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i_av_adr;
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input [P_AVALON_BE_WIDTH-1:0]
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input [P_AVALON_BE_WIDTH-1:0]
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i_av_be;
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i_av_be;
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input i_av_r;
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input i_av_r;
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output [P_AVALON_DATA_WIDTH-1:0]
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output [P_AVALON_DATA_WIDTH-1:0]
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o_av_rd;
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o_av_rd;
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input i_av_w;
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input i_av_w;
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input [P_AVALON_DATA_WIDTH-1:0]
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input [P_AVALON_DATA_WIDTH-1:0]
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i_av_wd;
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i_av_wd;
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output o_av_wait;
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output o_av_wait;
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// internal side
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// internal side
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output o_req;
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output o_req;
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output o_wr;
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output o_wr;
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output [P_INTERNAL_ADR_WIDTH-1:0]
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output [P_INTERNAL_ADR_WIDTH-1:0]
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o_adrs;
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o_adrs;
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input i_ack;
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input i_ack;
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output [P_INTERNAL_BE_WIDTH-1:0]
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output [P_INTERNAL_BE_WIDTH-1:0]
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o_be;
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o_be;
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output [P_INTERNAL_DATA_WIDTH-1:0]
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output [P_INTERNAL_DATA_WIDTH-1:0]
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o_wd;
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o_wd;
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input i_rstr;
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input i_rstr;
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input [P_INTERNAL_DATA_WIDTH-1:0]
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input [P_INTERNAL_DATA_WIDTH-1:0]
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i_rd;
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i_rd;
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//////////////////////////////////
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//////////////////////////////////
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// parameter definition
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// parameter definition
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//////////////////////////////////
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//////////////////////////////////
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localparam P_IDLE = 2'h0;
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localparam P_IDLE = 2'h0;
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localparam P_WAIT_ACK = 2'h1;
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localparam P_WAIT_ACK = 2'h1;
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localparam P_R_WAIT_RDATA = 2'h2;
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localparam P_R_WAIT_RDATA = 2'h2;
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localparam P_ACK_OUT = 2'h3;
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localparam P_ACK_OUT = 2'h3;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg [1:0] r_state;
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reg [1:0] r_state;
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reg r_req;
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reg r_req;
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reg r_wr;
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reg r_wr;
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reg [P_INTERNAL_ADR_WIDTH-1:0]
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reg [P_INTERNAL_ADR_WIDTH-1:0]
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r_adrs;
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r_adrs;
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reg [P_INTERNAL_DATA_WIDTH-1:0]
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reg [P_INTERNAL_DATA_WIDTH-1:0]
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r_rdata;
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r_rdata;
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reg [P_INTERNAL_BE_WIDTH-1:0]
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reg [P_INTERNAL_BE_WIDTH-1:0]
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r_be;
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r_be;
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reg [P_INTERNAL_DATA_WIDTH-1:0]
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reg [P_INTERNAL_DATA_WIDTH-1:0]
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r_wd;
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r_wd;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire [P_INTERNAL_ADR_WIDTH-1:0]
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wire [P_INTERNAL_ADR_WIDTH-1:0]
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w_adrs;
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w_adrs;
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wire [P_INTERNAL_DATA_WIDTH-1:0]
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wire [P_INTERNAL_DATA_WIDTH-1:0]
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w_rdata;
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w_rdata;
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wire [P_INTERNAL_BE_WIDTH-1:0]
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wire [P_INTERNAL_BE_WIDTH-1:0]
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w_be;
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w_be;
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wire [P_INTERNAL_DATA_WIDTH-1:0]
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wire [P_INTERNAL_DATA_WIDTH-1:0]
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w_wd;
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w_wd;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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generate
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generate
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if (P_INTERNAL_DATA_WIDTH == 'd8) begin
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if (P_INTERNAL_DATA_WIDTH == 'd8) begin
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wire [1:0] w_ba;
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wire [1:0] w_ba;
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assign o_av_rd = {'d4{r_rdata}};
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assign o_av_rd = {'d4{r_rdata}};
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assign w_ba = i_av_be[1] ? 2'd1 :
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assign w_ba = i_av_be[1] ? 2'd1 :
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i_av_be[2] ? 2'd2 :
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i_av_be[2] ? 2'd2 :
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i_av_be[3] ? 2'd3 :
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i_av_be[3] ? 2'd3 :
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2'd0 ;
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2'd0 ;
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assign w_adrs = {i_av_adr,w_ba};
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assign w_adrs = {i_av_adr,w_ba};
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assign w_be = i_av_be[w_ba];
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assign w_be = i_av_be[w_ba];
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assign w_wd = (w_ba == 'd1) ? i_av_wd[15:8]:
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assign w_wd = (w_ba == 'd1) ? i_av_wd[15:8]:
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(w_ba == 'd2) ? i_av_wd[23:16]:
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(w_ba == 'd2) ? i_av_wd[23:16]:
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(w_ba == 'd3) ? i_av_wd[31:24]:
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(w_ba == 'd3) ? i_av_wd[31:24]:
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i_av_wd[7:0];
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i_av_wd[7:0];
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end else begin
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end else begin
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assign o_av_rd = r_rdata;
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assign o_av_rd = r_rdata;
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assign w_adrs = i_av_adr;
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assign w_adrs = i_av_adr;
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assign w_be = i_av_be;
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assign w_be = i_av_be;
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assign w_wd = i_av_wd;
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assign w_wd = i_av_wd;
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end
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end
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endgenerate
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endgenerate
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assign o_req = r_req;
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assign o_req = r_req;
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assign o_wr = r_wr;
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assign o_wr = r_wr;
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assign o_adrs = r_adrs;
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assign o_adrs = r_adrs;
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assign o_be = r_be;
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assign o_be = r_be;
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assign o_wd = r_wd;
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assign o_wd = r_wd;
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assign o_av_wait = !(!(i_av_r|i_av_w) & (r_state == P_IDLE) |
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assign o_av_wait = !(!(i_av_r|i_av_w) & (r_state == P_IDLE) |
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(r_state == P_ACK_OUT));
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(r_state == P_ACK_OUT));
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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// core clock domain
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// core clock domain
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_req <= 1'b0;
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r_req <= 1'b0;
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r_wr <= 1'b0;
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r_wr <= 1'b0;
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r_adrs <= {P_INTERNAL_ADR_WIDTH{1'b0}};
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r_adrs <= {P_INTERNAL_ADR_WIDTH{1'b0}};
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r_rdata <= {P_INTERNAL_DATA_WIDTH{1'b0}};
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r_rdata <= {P_INTERNAL_DATA_WIDTH{1'b0}};
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r_be <= {P_INTERNAL_BE_WIDTH{1'b0}};
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r_be <= {P_INTERNAL_BE_WIDTH{1'b0}};
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r_wd <= {P_INTERNAL_DATA_WIDTH{1'b0}};
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r_wd <= {P_INTERNAL_DATA_WIDTH{1'b0}};
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: begin
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P_IDLE: begin
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if (i_av_w) begin
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if (i_av_w) begin
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// write
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// write
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r_req <= 1'b1;
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r_req <= 1'b1;
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r_wr <= 1'b1;
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r_wr <= 1'b1;
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r_adrs <= w_adrs;
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r_adrs <= w_adrs;
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r_be <= w_be;
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r_be <= w_be;
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r_wd <= w_wd;
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r_wd <= w_wd;
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r_state <= P_WAIT_ACK;
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r_state <= P_WAIT_ACK;
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end else if (i_av_r) begin
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end else if (i_av_r) begin
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// read
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// read
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r_req <= 1'b1;
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r_req <= 1'b1;
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r_wr <= 1'b0;
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r_wr <= 1'b0;
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r_adrs <= w_adrs;
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r_adrs <= w_adrs;
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r_state <= P_WAIT_ACK;
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r_state <= P_WAIT_ACK;
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end
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end
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end
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end
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P_WAIT_ACK: begin
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P_WAIT_ACK: begin
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if (i_ack) begin
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if (i_ack) begin
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r_req <= 1'b0;
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r_req <= 1'b0;
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if (r_wr) begin
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if (r_wr) begin
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// write
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// write
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r_state <= P_ACK_OUT;
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r_state <= P_ACK_OUT;
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end else begin
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end else begin
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if (i_rstr) begin
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if (i_rstr) begin
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r_rdata <= i_rd;
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r_rdata <= i_rd;
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r_state <= P_ACK_OUT;
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r_state <= P_ACK_OUT;
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end else begin
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end else begin
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r_state <= P_R_WAIT_RDATA;
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r_state <= P_R_WAIT_RDATA;
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end
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end
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end
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end
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end
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end
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end
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end
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P_R_WAIT_RDATA: begin
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P_R_WAIT_RDATA: begin
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if (i_rstr) begin
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if (i_rstr) begin
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r_rdata <= i_rd;
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r_rdata <= i_rd;
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r_state <= P_ACK_OUT;
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r_state <= P_ACK_OUT;
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end
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end
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end
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end
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P_ACK_OUT: begin
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P_ACK_OUT: begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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