//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_mem_arb.v
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// fm_mem_arb.v
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//
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//
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// Abstract:
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// Abstract:
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// Memory access arbiter.
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// Memory access arbiter.
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "fm_3d_define.v"
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`include "fm_3d_define.v"
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module fm_mem_arb (
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module fm_mem_arb (
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// system
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// system
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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// Geometry Engine
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// Geometry Engine
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input i_req_geo,
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input i_req_geo,
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input [31:0] i_adrs_geo,
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input [31:0] i_adrs_geo,
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input [2:0] i_len_geo,
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input [2:0] i_len_geo,
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output o_ack_geo,
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output o_ack_geo,
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// Rasterizer
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// Rasterizer
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input i_req_ras,
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input i_req_ras,
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input [31:0] i_adrs_ras,
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input [31:0] i_adrs_ras,
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output o_ack_ras,
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output o_ack_ras,
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// Memory I/F
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// Memory I/F
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output o_req_m,
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output o_req_m,
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output o_wr_m,
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output o_wr_m,
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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output [31:2] o_adrs_m,
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output [31:2] o_adrs_m,
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`else
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`else
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output [31:0] o_adrs_m,
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output [31:0] o_adrs_m,
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`endif
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`endif
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output [2:0] o_len_m,
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output [2:0] o_len_m,
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input i_ack_m
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input i_ack_m
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);
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);
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localparam P_IDLE = 'd0;
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localparam P_IDLE = 'd0;
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localparam P_WAIT = 'd1;
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localparam P_WAIT = 'd1;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg r_state;
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reg r_state;
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reg r_req_geo;
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reg r_req_geo;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_req;
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wire w_req;
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wire w_pri;
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wire w_pri;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign w_req = i_req_geo | i_req_ras;
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assign w_req = i_req_geo | i_req_ras;
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assign w_pri = (r_state == P_WAIT) ? r_req_geo : i_req_geo;
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assign w_pri = (r_state == P_WAIT) ? r_req_geo : i_req_geo;
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assign o_req_m = w_req;
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assign o_req_m = w_req;
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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assign o_adrs_m = (w_pri) ? i_adrs_geo[31:2] : i_adrs_ras[31:2];
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assign o_adrs_m = (w_pri) ? i_adrs_geo[31:2] : i_adrs_ras[31:2];
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`else
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`else
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assign o_adrs_m = (w_pri) ? i_adrs_geo : i_adrs_ras;
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assign o_adrs_m = (w_pri) ? i_adrs_geo : i_adrs_ras;
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`endif
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`endif
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assign o_len_m = (w_pri) ? i_len_geo : 3'd1;
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assign o_len_m = (w_pri) ? i_len_geo : 3'd1;
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assign o_ack_geo = i_ack_m & w_pri;
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assign o_ack_geo = i_ack_m & w_pri;
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assign o_ack_ras = i_ack_m & !w_pri;
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assign o_ack_ras = i_ack_m & !w_pri;
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assign o_wr_m = ~w_pri;
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assign o_wr_m = ~w_pri;
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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`ifdef D3D_SYNC_RESET
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`ifdef D3D_SYNC_RESET
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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`else
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`else
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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`endif
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`endif
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if (rst_x == `D3D_RESET_POL) begin
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if (rst_x == `D3D_RESET_POL) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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r_req_geo <= 1'b0;
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r_req_geo <= 1'b0;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE:begin
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P_IDLE:begin
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if (w_req) begin
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if (w_req) begin
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if (!i_ack_m) begin
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if (!i_ack_m) begin
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r_req_geo <= i_req_geo;
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r_req_geo <= i_req_geo;
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r_state <= P_WAIT;
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r_state <= P_WAIT;
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end
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end
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end
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end
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end
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end
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P_WAIT:begin
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P_WAIT:begin
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if (i_ack_m) r_state <= P_IDLE;
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if (i_ack_m) r_state <= P_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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