//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_ras.v
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// fm_ras.v
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//
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//
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// Abstract:
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// Abstract:
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// Rasterizer top module.
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// Rasterizer top module.
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "fm_3d_define.v"
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`include "fm_3d_define.v"
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module fm_ras (
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module fm_ras (
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// system
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// system
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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// Register Configuration
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// Register Configuration
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input [15:0] i_scr_w_m1,
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input [15:0] i_scr_w_m1,
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input [15:0] i_scr_h_m1,
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input [15:0] i_scr_h_m1,
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input [15:0] i_scr_w,
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input [15:0] i_scr_w,
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input [29:0] i_pixel_top_address,
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input [29:0] i_pixel_top_address,
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input [7:0] i_pixel_color,
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input [7:0] i_pixel_color,
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input i_y_flip,
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input i_y_flip,
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// Geometry Engine I/F
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// Geometry Engine I/F
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(* mark_debug = "true" *) input i_en,
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(* mark_debug = "true" *) input i_en,
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(* mark_debug = "true" *) output o_ack,
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(* mark_debug = "true" *) output o_ack,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v0_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v0_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v0_y,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v0_y,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v1_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v1_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v1_y,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v1_y,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v2_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v2_x,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v2_y,
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(* mark_debug = "true" *) input [`D3D_FTOI_WIDTH-1:0] i_v2_y,
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(* mark_debug = "true" *) output o_ras_state,
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(* mark_debug = "true" *) output o_ras_state,
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// Pixel Write Memory I/F (Write Only)
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// Pixel Write Memory I/F (Write Only)
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output o_req_m,
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output o_req_m,
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output [31:0] o_adrs_m,
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output [31:0] o_adrs_m,
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input i_ack_m,
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input i_ack_m,
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output [3:0] o_be_m,
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output [3:0] o_be_m,
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output [31:0] o_dbw_m
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output [31:0] o_dbw_m
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_en;
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wire w_en;
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wire w_ack;
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wire w_ack;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v0_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_v1_y;
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wire w_en_pix;
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wire w_en_pix;
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wire w_ack_pix;
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wire w_ack_pix;
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wire [`D3D_FTOI_WIDTH-1:0] w_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_x;
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wire [`D3D_FTOI_WIDTH-1:0] w_y;
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wire [`D3D_FTOI_WIDTH-1:0] w_y;
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wire w_state_line;
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wire w_state_line;
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//////////////////////////////////
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//////////////////////////////////
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// module instance
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// module instance
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//////////////////////////////////
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//////////////////////////////////
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fm_ras_state u_ras_state (
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fm_ras_state u_ras_state (
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// system
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// system
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// Register Configuration
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// Register Configuration
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.i_scr_w_m1(i_scr_w_m1),
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.i_scr_w_m1(i_scr_w_m1),
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.i_scr_h_m1(i_scr_h_m1),
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.i_scr_h_m1(i_scr_h_m1),
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// Vertex input
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// Vertex input
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.i_en(i_en),
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.i_en(i_en),
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.o_ack(o_ack),
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.o_ack(o_ack),
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.i_v0_x(i_v0_x),
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.i_v0_x(i_v0_x),
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.i_v0_y(i_v0_y),
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.i_v0_y(i_v0_y),
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.i_v1_x(i_v1_x),
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.i_v1_x(i_v1_x),
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.i_v1_y(i_v1_y),
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.i_v1_y(i_v1_y),
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.i_v2_x(i_v2_x),
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.i_v2_x(i_v2_x),
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.i_v2_y(i_v2_y),
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.i_v2_y(i_v2_y),
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.o_ras_state(o_ras_state),
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.o_ras_state(o_ras_state),
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// Current Line
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// Current Line
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.o_en(w_en),
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.o_en(w_en),
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.i_ack(w_ack),
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.i_ack(w_ack),
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.o_v0_x(w_v0_x),
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.o_v0_x(w_v0_x),
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.o_v0_y(w_v0_y),
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.o_v0_y(w_v0_y),
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.o_v1_x(w_v1_x),
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.o_v1_x(w_v1_x),
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.o_v1_y(w_v1_y),
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.o_v1_y(w_v1_y),
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.i_state(w_state_line)
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.i_state(w_state_line)
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);
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);
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fm_ras_line u_ras_line (
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fm_ras_line u_ras_line (
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// system
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// system
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.o_state(w_state_line),
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.o_state(w_state_line),
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// Register Configuration
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// Register Configuration
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.i_scr_w_m1(i_scr_w_m1),
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.i_scr_w_m1(i_scr_w_m1),
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.i_scr_h_m1(i_scr_h_m1),
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.i_scr_h_m1(i_scr_h_m1),
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// Vertex input
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// Vertex input
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.i_en(w_en),
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.i_en(w_en),
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.o_ack(w_ack),
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.o_ack(w_ack),
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.i_v0_x(w_v0_x),
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.i_v0_x(w_v0_x),
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.i_v0_y(w_v0_y),
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.i_v0_y(w_v0_y),
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.i_v1_x(w_v1_x),
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.i_v1_x(w_v1_x),
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.i_v1_y(w_v1_y),
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.i_v1_y(w_v1_y),
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// Pixel out
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// Pixel out
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.o_en(w_en_pix),
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.o_en(w_en_pix),
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.i_ack(w_ack_pix),
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.i_ack(w_ack_pix),
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.o_x(w_x),
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.o_x(w_x),
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.o_y(w_y)
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.o_y(w_y)
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);
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);
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fm_ras_mem u_ras_mem (
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fm_ras_mem u_ras_mem (
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// system
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// system
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_y_flip(i_y_flip),
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.i_y_flip(i_y_flip),
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// Register Configuration
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// Register Configuration
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.i_scr_w(i_scr_w),
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.i_scr_w(i_scr_w),
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.i_scr_h_m1(i_scr_h_m1),
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.i_scr_h_m1(i_scr_h_m1),
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.i_pixel_top_address(i_pixel_top_address),
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.i_pixel_top_address(i_pixel_top_address),
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.i_pixel_color(i_pixel_color),
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.i_pixel_color(i_pixel_color),
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// Pixel In
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// Pixel In
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.i_en(w_en_pix),
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.i_en(w_en_pix),
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.o_ack(w_ack_pix),
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.o_ack(w_ack_pix),
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.i_x(w_x),
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.i_x(w_x),
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.i_y(w_y),
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.i_y(w_y),
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// Pixel Write Memory I/F (Write Only)
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// Pixel Write Memory I/F (Write Only)
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.o_req_m(o_req_m),
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.o_req_m(o_req_m),
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.o_adrs_m(o_adrs_m),
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.o_adrs_m(o_adrs_m),
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.i_ack_m(i_ack_m),
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.i_ack_m(i_ack_m),
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.o_be_m(o_be_m),
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.o_be_m(o_be_m),
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.o_dbw_m(o_dbw_m)
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.o_dbw_m(o_dbw_m)
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);
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);
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endmodule
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endmodule
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