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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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January 27,2013
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RTL - Commited changes to detect PC underflow/overflow as an OP-code error.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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November 21,2011
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November 21,2011
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RTL - No Change
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RTL - No Change
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Code cleanup, converted tabs to blanks. Added code to instruction test to cover
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Code cleanup, converted tabs to blanks. Added code to instruction test to cover
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a few base instructions that weren't being tested. Changed instance name of
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a few base instructions that weren't being tested. Changed instance name of
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semaphore registers from "bit" to "sbit" to be compatible with System Verilog.
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semaphore registers from "bit" to "sbit" to be compatible with System Verilog.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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My current idea list for enhancements is:
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My current idea list for enhancements is:
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Add to the software apps:
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Add to the software apps:
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a - It should be possible to write software to emulate some simple hardware modules such as I2C, SPI and UART.
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a - It should be possible to write software to emulate some simple hardware
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modules such as I2C, SPI and UART.
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b - DMA controller software
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b - DMA controller software
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c - Find open source C compiler for Xgate
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c - Find open source C compiler for Xgate
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d - ???
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d - ???
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It would be interesting to integrate the Xgate with some of the other OpenCores peripheral modules. Again there would be some related software development for verification. The ultimate goal would be to to create full-blown drivers for these modules.
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It would be interesting to integrate the Xgate with some of the other OpenCores
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a - Integrate Xgate with I2C controller and develop software to support SMBus and PMBus protocols.
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peripheral modules. Again there would be some related software development for
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verification. The ultimate goal would be to to create full-blown drivers for
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these modules.
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a - Integrate Xgate with I2C controller and develop software to support
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SMBus and PMBus protocols.
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b - ???
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b - ???
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Another interesting integration project would be to build a processor core with the OpenRISC as the host and the Xgate working as a co-processor. Some type of memory controller module would need to be developed so the Xgate could have some semiprivate RAM to run code from. Also a separate slave bus would be nice to isolate peripherals that could be managed mostly by the Xgate. Some software development would be required for both OpenRISC and Xgate to verify the functionality.
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Another interesting integration project would be to build a processor core with
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the OpenRISC as the host and the Xgate working as a co-processor. Some type of
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Develop hardware debug module. Survey Freescale debugger and other debugger specifications and develop hardware debugger/specification that can optionally be connected to the Xgate module. The debugger should be broken into at least two modules, one the actual debug interface and the second a flexible serial interface adaptor. There are already JTAG modules in the design database that I had thought might be used as one possible interface to the debugger. (A great project on it's own would be to develop a JTAG module that meets the latest JTAG specification including the single wire interface.)
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memory controller module would need to be developed so the Xgate could have
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some semiprivate RAM to run code from. Also a separate slave bus would be
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Upgrade Xgate to the enhanced version that Freescale now ships. This includes an alternate register set so the Xgate can switch in a few cycles from a low priority interrupt to a higher priority interrupt and then return to the low priority interrupt process.
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nice to isolate peripherals that could be managed mostly by the Xgate. Some
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software development would be required for both OpenRISC and Xgate to verify
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Improvements to the architecture to support high speed operation. The current code was developed in a piecemeal fashion without much pre-planing on the data path from/to RAM and the internal registers.
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the functionality.
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Develop hardware debug module. Survey Freescale debugger and other debugger
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specifications and develop hardware debugger/specification that can optionally
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be connected to the Xgate module. The debugger should be broken into at least
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two modules, one the actual debug interface and the second a flexible serial
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interface adaptor. There are already JTAG modules in the design database that
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I had thought might be used as one possible interface to the debugger.
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(A great project on it's own would be to develop a JTAG module that meets the
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latest JTAG specification including the single wire interface.)
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Upgrade Xgate to the enhanced version that Freescale now ships. This includes
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an alternate register set so the Xgate can switch in a few cycles from a low
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priority interrupt to a higher priority interrupt and then return to the low
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priority interrupt process.
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Improvements to the architecture to support high speed operation. The current
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code was developed in a piecemeal fashion without much pre-planing on the
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data path from/to RAM and the internal registers.
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System Verilog class based constrained random verification environment.
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System Verilog class based constrained random verification environment.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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August 11,2010
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August 11,2010
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RTL - No Change
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RTL - No Change
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Applications - Added the "application" directory to the "sw" directory. The
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Applications - Added the "application" directory to the "sw" directory. The
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first application code added is the SKIPJACK encrypt/decrypt function. This
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first application code added is the SKIPJACK encrypt/decrypt function. This
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algorithm works on a 64 bit block of data and uses an 80 bit key. See the
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algorithm works on a 64 bit block of data and uses an 80 bit key. See the
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"sw/applications/skipjack/README.txt" file for more information.
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"sw/applications/skipjack/README.txt" file for more information.
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Testbench - To aid in software development a simple debug module was added to
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Testbench - To aid in software development a simple debug module was added to
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the testbench. The debugger loads watchpoint addresses stored in RAM after
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the testbench. The debugger loads watchpoint addresses stored in RAM after
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the first RAM initialization. The debugger generates trigger signals that
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the first RAM initialization. The debugger generates trigger signals that
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can be watched in the waveform viewer and captures a copy of the CPU
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can be watched in the waveform viewer and captures a copy of the CPU
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registers at each trigger event. The watch point addresses are captured by
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registers at each trigger event. The watch point addresses are captured by
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the assembler and stored in RAM addresses reserved for the test bench.
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the assembler and stored in RAM addresses reserved for the test bench.
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There are enable registers in the testbench that can enable or disable any
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There are enable registers in the testbench that can enable or disable any
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of the eight individual watchpoints under testbench control.
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of the eight individual watchpoints under testbench control.
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Doc - Made corrections to some of the example code in the detailed instruction
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Doc - Made corrections to some of the example code in the detailed instruction
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descriptions.
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descriptions.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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June 10,2010
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June 10,2010
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RTL - No Change
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RTL - No Change
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Testbench - No Change.
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Testbench - No Change.
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Doc - Added descriptions for interrupt bypass registers. Added Appendix B for
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Doc - Added descriptions for interrupt bypass registers. Added Appendix B for
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testbench description.
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testbench description.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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May 18,2010
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May 18,2010
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RTL - Fixed xlink synthesis warnings noted by Nachiket Jugade,
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RTL - Fixed xlink synthesis warnings noted by Nachiket Jugade,
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missing else statment for chid_sm_ns line 393,
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missing else statment for chid_sm_ns line 393,
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missing default on shifter lines 2382 (Although all cases are covered).
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missing default on shifter lines 2382 (Although all cases are covered).
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Testbench - No Change.
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Testbench - No Change.
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Doc - No Change.
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Doc - No Change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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May 13,2010
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May 13,2010
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RTL - Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and
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RTL - Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and
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input pins along with assoicated status and and control registers. This
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input pins along with assoicated status and and control registers. This
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channel has never been usable.
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channel has never been usable.
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Testbench - Changes to match changes in RTL .
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Testbench - Changes to match changes in RTL .
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Doc - No Change.
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Doc - No Change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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May 12,2010
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May 12,2010
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RTL - Added new control registers for interrupt bypass function. Out of reset
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RTL - Added new control registers for interrupt bypass function. Out of reset
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all input interrupts are bypassed directly to the Xgate interrupt outputs.
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all input interrupts are bypassed directly to the Xgate interrupt outputs.
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The interrupts are also disabled from effecting the Xgate till the bypass
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The interrupts are also disabled from effecting the Xgate till the bypass
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is disabled. The interrupt priority has been flipped so that now the lowest
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is disabled. The interrupt priority has been flipped so that now the lowest
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index input interrupt has the highest priority.
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index input interrupt has the highest priority.
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Testbench - Added semaphore register and read only registers to observe irq
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Testbench - Added semaphore register and read only registers to observe irq
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outputs of Xgate to testbench slave module. Added parameters to support new
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outputs of Xgate to testbench slave module. Added parameters to support new
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Xgate registers and testbench registers. Added new test to checkout
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Xgate registers and testbench registers. Added new test to checkout
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bypass functionality and interrupt priority encoding.
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bypass functionality and interrupt priority encoding.
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Doc - Updated with additions of IRQ Bypass registers.
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Doc - Updated with additions of IRQ Bypass registers.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 22,2010
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Apr 22,2010
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RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
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RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
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All tests now pass when the RAM wait states are set from zero to four. Five
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All tests now pass when the RAM wait states are set from zero to four. Five
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wait states times out in simulation while running the last test which is
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wait states times out in simulation while running the last test which is
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a simple register test otherwise I expect it would pass.
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a simple register test otherwise I expect it would pass.
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Testbench - Many of the failures while testing wait states were due to fixed
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Testbench - Many of the failures while testing wait states were due to fixed
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delays coded in the testbench. As necessary, delays were changed to be a
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delays coded in the testbench. As necessary, delays were changed to be a
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function of a parameter that is based on the number of RAM wait states.
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function of a parameter that is based on the number of RAM wait states.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 5,2010
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Apr 5,2010
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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although there are errors in DEBUG mode when RAM wait states are increased.
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although there are errors in DEBUG mode when RAM wait states are increased.
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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now used to instantiate the semaphore registers.
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now used to instantiate the semaphore registers.
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Testbench - Added capability to insert wait states on RAM access.
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Testbench - Added capability to insert wait states on RAM access.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Feb 12,2010
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Feb 12,2010
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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16 data flops for 5 address registers. This change now also requires single
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16 data flops for 5 address registers. This change now also requires single
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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cycles required the address to be decoded and the read data to be latched
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cycles required the address to be decoded and the read data to be latched
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in the first cycle and the there was a whole cycle to drive the read data
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in the first cycle and the there was a whole cycle to drive the read data
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bus. The new design latches the address in the first cycle then decodes the
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bus. The new design latches the address in the first cycle then decodes the
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address and outputs the data in the second cycle. (The WISHBONE bus doesn't
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address and outputs the data in the second cycle. (The WISHBONE bus doesn't
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require the address or data to be latched for multi-cycle operation but by
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require the address or data to be latched for multi-cycle operation but by
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doing this it is hoped some power will be saved in the combinational logic
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doing this it is hoped some power will be saved in the combinational logic
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by reducing the decoding activity at each address change.)
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by reducing the decoding activity at each address change.)
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Testbench - No change.
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Testbench - No change.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Jan 27,2010
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Jan 27,2010
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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enabled. If a slave bus transaction was started but not completed in the
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enabled. If a slave bus transaction was started but not completed in the
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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signal to flag this input condition but not sure if it is really needed.
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signal to flag this input condition but not sure if it is really needed.
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The old testbench was "helping" the Xgate module by sending an almost
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The old testbench was "helping" the Xgate module by sending an almost
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continuous wbm_ack_i signal which allowed the RISC state machine to advance
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continuous wbm_ack_i signal which allowed the RISC state machine to advance
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when it shouldn't. Changes were made to the WISHBONE master bus interface
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when it shouldn't. Changes were made to the WISHBONE master bus interface
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and the RISC control logic.
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and the RISC control logic.
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Updates to testbench -- Extensive changes to testbench. The bus arbitration
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Updates to testbench -- Extensive changes to testbench. The bus arbitration
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module has been completely rewritten. It now completely controls access to the
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module has been completely rewritten. It now completely controls access to the
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system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
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system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
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The test control registers have been moved out of the top level and put into
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The test control registers have been moved out of the top level and put into
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a new WISHBONE slave module which also attaches to the system bus. The Xgate
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a new WISHBONE slave module which also attaches to the system bus. The Xgate
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modules master and slave buses are fully integrated with the bus arbitration
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modules master and slave buses are fully integrated with the bus arbitration
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module and the system bus. The new testbench looks a lot more like a real
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module and the system bus. The new testbench looks a lot more like a real
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system environment.
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system environment.
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To Do: Add back "random" wait state generation for RAM access.
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To Do: Add back "random" wait state generation for RAM access.
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Updates to User Guide -- Minor corrections to instruction set details. Needs more
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Updates to User Guide -- Minor corrections to instruction set details. Needs more
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review on condition code settings.
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Jan 11,2010
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Jan 11,2010
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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There is a bug in DEBUG mode that is sensitive to number of preceding
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There is a bug in DEBUG mode that is sensitive to number of preceding
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instructions and wait states that needs to be resolved.
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instructions and wait states that needs to be resolved.
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Updates to testbench --
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Updates to testbench --
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Updates to User Guide -- First pass with instruction set details. Needs more
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Updates to User Guide -- First pass with instruction set details. Needs more
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review on condition code settings.
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Dec 08,2009
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Dec 08,2009
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RTL - 85% done -- Updated code so there is only one program counter adder.
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RTL - 85% done -- Updated code so there is only one program counter adder.
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Updated WISHBONE Slave bus for word addressability and byte selection.
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Updated WISHBONE Slave bus for word addressability and byte selection.
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Deleted two stack pointer registers.
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Deleted two stack pointer registers.
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Updates to testbench --
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Updates to testbench --
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Updates to User Guide -- Minor cleanup.
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Updates to User Guide -- Minor cleanup.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Nov 09,2009
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Nov 09,2009
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RTL - 85% done - Minor changes to Mastermode bus.
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RTL - 85% done - Minor changes to Mastermode bus.
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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but this is not fully functional. Causes timing problems when master is
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but this is not fully functional. Causes timing problems when master is
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polling Xgate registers durning debug mode tests. Will probably change RAM
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polling Xgate registers durning debug mode tests. Will probably change RAM
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model to dual port in next revision.
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model to dual port in next revision.
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Updated master module to include WISHBONE select inputs.
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Updated master module to include WISHBONE select inputs.
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Updates to User Guide.
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Updates to User Guide.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Oct 07,2009
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Oct 07,2009
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RTL - 85% done
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RTL - 85% done
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All debug commands now working, including writes to XGCHID register.
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All debug commands now working, including writes to XGCHID register.
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Updates to testbench, added timeout and total error count.
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Updates to testbench, added timeout and total error count.
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Updates to User Guide --.
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Updates to User Guide --.
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Created the sw directory and copied over the software stuff from the bench
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Created the sw directory and copied over the software stuff from the bench
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directory.
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directory.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 23,2009
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Sept 23,2009
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BRK instruction working. Single Step Command in debug mode working.
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BRK instruction working. Single Step Command in debug mode working.
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Software error interrupt added.
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Software error interrupt added.
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Updates to testbench.
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Updates to testbench.
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New assembly code directory: debug_test
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New assembly code directory: debug_test
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 10,2009
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Sept 10,2009
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Added WISHBONE master bus submodule and some related top level signals but still
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Added WISHBONE master bus submodule and some related top level signals but still
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not much real functionality.
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not much real functionality.
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Added code to allow for memory access stalls.
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Added code to allow for memory access stalls.
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Upgraded testbench to insert memory wait states. Added more error detection
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Upgraded testbench to insert memory wait states. Added more error detection
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and summery.
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and summery.
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Improved instruction decoder. Still needs more work to remove redundant adders
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Improved instruction decoder. Still needs more work to remove redundant adders
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to improve synthesis results.
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to improve synthesis results.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 1, 2009
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Sept 1, 2009
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This is a prerelease checkin and should be looked at as an incremental backup
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This is a prerelease checkin and should be looked at as an incremental backup
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and not representative of what may be in the final release.
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and not representative of what may be in the final release.
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RTL - 75% done
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RTL - 75% done
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What works:
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What works:
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Basic instruction set execution simulated and verified. Condition code
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Basic instruction set execution simulated and verified. Condition code
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operation on instructions partially verified.
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operation on instructions partially verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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What's broken or unimplemented:
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What's broken or unimplemented:
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All things related to debug mode.
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All things related to debug mode.
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WISHBONE master bus interface.
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WISHBONE master bus interface.
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User Documentation - 30% done
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User Documentation - 30% done
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