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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/fault_sm.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/fault_sm.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_small.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_small.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_medium.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_mem_medium.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo_ctrl.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo_ctrl.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/generic_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync_single.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/meta_sync_single.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_hold_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_hold_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_data_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_data_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_dequeue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_dequeue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_enqueue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/rx_enqueue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_core.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_core.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_wb.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_wb.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_xgmii_tx.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/sync_clk_xgmii_tx.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_hold_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_hold_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_data_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_data_fifo.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_dequeue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_dequeue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.v
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vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.sv
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vsim -voptargs="+acc" work.tb
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vsim -voptargs="+acc" work.tb
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add wave sim:/tb/*
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add wave sim:/tb/*
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add wave -divider
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add wave -divider
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add wave sim:/tb/dut/*
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add wave sim:/tb/dut/*
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add wave -divider
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add wave -divider
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add wave sim:/tb/dut/rx_eq0/*
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add wave sim:/tb/dut/rx_eq0/*
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add wave -divider
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add wave -divider
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add wave sim:/tb/dut/rx_data_fifo0/*
|
add wave sim:/tb/dut/rx_data_fifo0/*
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add wave -divider
|
add wave -divider
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add wave sim:/tb/dut/rx_dq0/*
|
add wave sim:/tb/dut/rx_dq0/*
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|
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add wave -divider
|
add wave -divider
|
add wave -divider
|
add wave -divider
|
add wave -divider
|
add wave -divider
|
|
|
add wave sim:/tb/dut/tx_eq0/*
|
add wave sim:/tb/dut/tx_eq0/*
|
|
|
add wave -divider
|
add wave -divider
|
|
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add wave sim:/tb/dut/tx_data_fifo0/*
|
add wave sim:/tb/dut/tx_data_fifo0/*
|
|
|
add wave -divider
|
add wave -divider
|
|
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add wave sim:/tb/dut/tx_dq0/*
|
add wave sim:/tb/dut/tx_dq0/*
|
|
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add wave -divider
|
add wave -divider
|
|
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add wave sim:/tb/dut/fault_sm0/*
|
add wave sim:/tb/dut/fault_sm0/*
|
|
|
add wave -divider
|
add wave -divider
|
|
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add wave sim:/tb/dut/wishbone_if0/*
|
add wave sim:/tb/dut/wishbone_if0/*
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#run 1000ns
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#run 1000ns
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