`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company: UPT
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// Engineer:
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// Engineer: Constantina-Elena Gavriliu
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//
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//
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// Create Date: 18:50:09 10/17/2013
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// Create Date: 18:50:09 10/17/2013
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// Design Name:
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// Design Name:
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// Module Name: leading_zeros
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// Module Name: leading_zeros
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies: d_ff.v
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits
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module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits
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parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)
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parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)
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parameter PIPELINE = 2)
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parameter PIPELINE = 2)
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(a, ovf, lz);
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(a, ovf, lz);
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input [SIZE_INT-1:0] a;
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input [SIZE_INT-1:0] a;
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input ovf;
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input ovf;
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output [SIZE_COUNTER-1:0] lz;
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output [SIZE_COUNTER-1:0] lz;
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parameter nr_levels = SIZE_COUNTER - 1;
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parameter nr_levels = SIZE_COUNTER - 1;
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parameter max_pow_2 = 2 ** SIZE_COUNTER;
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parameter max_pow_2 = 2 ** SIZE_COUNTER;
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parameter size_lz = SIZE_COUNTER;
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parameter size_lz = SIZE_COUNTER;
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wire [max_pow_2-1:0] a_complete;
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wire [max_pow_2-1:0] a_complete;
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wire [max_pow_2-1:0] v_d[nr_levels-1:0];
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wire [max_pow_2-1:0] v_d[nr_levels-1:0];
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wire [max_pow_2-1:0] v_q[nr_levels-1:0];
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wire [max_pow_2-1:0] v_q[nr_levels-1:0];
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wire [max_pow_2-1:0] p_d[nr_levels-1:0];
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wire [max_pow_2-1:0] p_d[nr_levels-1:0];
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wire [max_pow_2-1:0] p_q[nr_levels-1:0];
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wire [max_pow_2-1:0] p_q[nr_levels-1:0];
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wire [size_lz-1:0] lzc;
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wire [size_lz-1:0] lzc;
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assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
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assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
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generate
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generate
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if (max_pow_2 != SIZE_INT)
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if (max_pow_2 != SIZE_INT)
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begin : gen_if
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begin : gen_if
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assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
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assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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begin : level_0
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begin : level_0
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genvar i;
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genvar i;
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for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
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for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
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begin : level_0
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begin : level_0
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assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
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assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
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assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
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assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
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(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
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(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
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(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
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(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
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end
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end
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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begin : level_generation_begin
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begin : level_generation_begin
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genvar i;
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genvar i;
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for (i = 1; i <= nr_levels - 1; i = i + 1)
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for (i = 1; i <= nr_levels - 1; i = i + 1)
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begin : level_generation
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begin : level_generation
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//begin : v_levels_begin
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genvar j;
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genvar j;
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for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
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for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
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begin : v_levels
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begin : v_levels
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assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
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assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
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end
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end
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//end
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//begin : p_levels_begin
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// genvar j;
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for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
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for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
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begin : p_levels
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begin : p_levels
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assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
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assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
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assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
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assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
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end
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end
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//end
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end
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end
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (PIPELINE != 0)
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if (PIPELINE != 0)
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begin : pipeline_stages
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begin : pipeline_stages
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//begin : INSERTION_begin
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genvar i;
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genvar i;
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for (i = 0; i <= nr_levels - 2; i = i + 1)
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for (i = 0; i <= nr_levels - 2; i = i + 1)
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begin : INSERTION
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begin : INSERTION
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if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
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if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
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begin : INS
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begin : INS
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d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
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d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
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d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
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d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
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end
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end
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if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
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if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
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begin : NO_INS
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begin : NO_INS
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assign p_q[i] = p_d[i];
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assign p_q[i] = p_d[i];
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assign v_q[i] = v_d[i];
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assign v_q[i] = v_d[i];
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end
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end
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end
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end
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//end
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assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
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assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
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assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
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assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (PIPELINE == 0)
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if (PIPELINE == 0)
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begin : no_pipeline
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begin : no_pipeline
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//begin : xhdl4
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genvar i;
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genvar i;
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for (i = 0; i <= nr_levels - 1; i = i + 1)
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for (i = 0; i <= nr_levels - 1; i = i + 1)
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begin : NO_INSERTION
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begin : NO_INSERTION
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assign p_q[i] = p_d[i];
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assign p_q[i] = p_d[i];
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assign v_q[i] = v_d[i];
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assign v_q[i] = v_d[i];
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end
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end
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//end
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end
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end
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endgenerate
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endgenerate
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assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
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assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
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generate
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generate
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begin : lz_ovf_begin
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begin : lz_ovf_begin
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genvar i;
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genvar i;
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for (i = 0; i <= size_lz - 1; i = i + 1)
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for (i = 0; i <= size_lz - 1; i = i + 1)
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begin : lz_ovf
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begin : lz_ovf
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assign lz[i] = lzc[i] & ((~ovf));
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assign lz[i] = lzc[i] & ((~ovf));
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end
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end
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end
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end
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endgenerate
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endgenerate
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