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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company: UPT
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// Engineer:
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// Engineer: Constantina-Elena Gavriliu
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//
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//
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// Create Date: 18:00:33 10/15/2013
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// Create Date: 18:00:33 10/15/2013
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// Design Name:
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// Design Name:
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// Module Name: shifter
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// Module Name: shifter
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies: d_ff.v
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module shifter #( parameter INPUT_SIZE = 13,
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module shifter #( parameter INPUT_SIZE = 13,
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parameter SHIFT_SIZE = 4,
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parameter SHIFT_SIZE = 4,
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parameter OUTPUT_SIZE = 24, //>INPUT_SIZE
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parameter OUTPUT_SIZE = 24, //>INPUT_SIZE
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parameter DIRECTION = 1,
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parameter DIRECTION = 1,
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parameter PIPELINE = 1,
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parameter PIPELINE = 1,
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parameter [7:0] POSITION = 8'b00000000)
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parameter [7:0] POSITION = 8'b00000000)
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(a, arith, shft, shifted_a);
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(a, arith, shft, shifted_a);
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input [INPUT_SIZE-1:0] a;
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input [INPUT_SIZE-1:0] a;
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input arith;
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input arith;
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input [SHIFT_SIZE-1:0] shft;
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input [SHIFT_SIZE-1:0] shft;
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output [OUTPUT_SIZE-1:0] shifted_a;
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output [OUTPUT_SIZE-1:0] shifted_a;
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wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];
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wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];
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wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];
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wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];
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assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
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assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
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assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
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assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
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generate
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generate
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begin : GENERATING
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begin : GENERATING
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genvar i;
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genvar i;
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for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
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for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
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begin : BARREL_SHIFTER_GENERATION
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begin : BARREL_SHIFTER_GENERATION
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if (DIRECTION == 1)
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if (DIRECTION == 1)
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begin : LEFT
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begin : LEFT
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//begin : 1st_check
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genvar j;
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genvar j;
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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begin : MUX_GEN_L
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begin : MUX_GEN_L
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if (j < 2 ** i)
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if (j < 2 ** i)
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begin : ZERO_INS_L
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begin : ZERO_INS_L
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
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end
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end
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if (j >= 2 ** i)
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if (j >= 2 ** i)
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begin : BIT_INS_L
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begin : BIT_INS_L
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
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end
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end
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end
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end
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//end
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end
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end
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if (DIRECTION == 0)
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if (DIRECTION == 0)
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begin : RIGHT
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begin : RIGHT
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//begin : 2nd_check
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genvar j;
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genvar j;
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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begin : MUX_GEN_R
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begin : MUX_GEN_R
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if (OUTPUT_SIZE - 1 < 2 ** i + j)
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if (OUTPUT_SIZE - 1 < 2 ** i + j)
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begin : ZERO_INS_R
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begin : ZERO_INS_R
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
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end
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end
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if (OUTPUT_SIZE - 1 >= 2 ** i + j)
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if (OUTPUT_SIZE - 1 >= 2 ** i + j)
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begin : BIT_INS_R
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begin : BIT_INS_R
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
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end
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end
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end
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end
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//end
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end
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end
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if (PIPELINE != 0)
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if (PIPELINE != 0)
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begin : PIPELINE_INSERTION
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begin : PIPELINE_INSERTION
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if (POSITION[i] == 1'b1)
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if (POSITION[i] == 1'b1)
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begin : LATCH
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begin : LATCH
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d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
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d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
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end
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end
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if (POSITION[i] == 1'b0)
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if (POSITION[i] == 1'b0)
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begin : NO_LATCH
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begin : NO_LATCH
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assign a_temp_q[i + 1] = a_temp_d[i];
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assign a_temp_q[i + 1] = a_temp_d[i];
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end
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end
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end
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end
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if (PIPELINE == 0)
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if (PIPELINE == 0)
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begin : NO_PIPELINE
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begin : NO_PIPELINE
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assign a_temp_q[i + 1] = a_temp_d[i];
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assign a_temp_q[i + 1] = a_temp_d[i];
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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assign shifted_a = a_temp_q[SHIFT_SIZE];
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assign shifted_a = a_temp_q[SHIFT_SIZE];
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endmodule
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endmodule
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