| Line 35... |
Line 35... |
next_state, // next state to exit to from the read from [PC] state machine
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next_state, // next state to exit to from the read from [PC] state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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next_push_state; // next state to exit to from push multiple state machine
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next_push_state; // next state to exit to from push multiple state machine
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reg k_write_tfr, k_write_exg;
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reg k_write_tfr, k_write_exg;
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reg k_cpu_oe, k_cpu_we, k_inc_pc;
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reg k_cpu_oe, k_cpu_we, k_inc_pc;
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|
reg k_indirect_loaded; // set when in indirect indexed and the address has been loaded
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reg [15:0] k_cpu_addr, k_new_pc;
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reg [15:0] k_cpu_addr, k_new_pc;
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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reg [1:0] k_mem_dest;
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reg [1:0] k_mem_dest;
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reg k_mul_cnt; // multiplier couner
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reg k_mul_cnt; // multiplier couner
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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| Line 571... |
Line 572... |
endcase
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endcase
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end
|
end
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`DIRECT:
|
`DIRECT:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
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state <= `SEQ_PC_READ_L; // loads address
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if (dec_o_p1_optype == `OP_JSR) // jsr
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case (dec_o_p1_optype)
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begin
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
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next_state <= `SEQ_JSR_PUSH;
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`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
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end
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default:
|
else
|
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begin
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begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
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k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
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if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
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if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
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(dec_o_left_path_addr == `RN_MEM8))
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(dec_o_left_path_addr == `RN_MEM8))
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begin
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begin
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| Line 588... |
Line 588... |
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
k_eahi <= regs_o_dp;
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k_eahi <= regs_o_dp;
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end
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end
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|
endcase
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end
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end
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`INDEXED:
|
`INDEXED:
|
state <= `SEQ_IND_READ_EA;
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state <= `SEQ_IND_READ_EA;
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`EXTENDED:
|
`EXTENDED:
|
begin
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begin
|
state <= `SEQ_PC_READ_H; // loads address
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state <= `SEQ_PC_READ_H; // loads address
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if (dec_o_p1_optype == `OP_JSR) // jsr
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case (dec_o_p1_optype)
|
begin
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
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next_state <= `SEQ_JSR_PUSH;
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`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
|
end
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default:
|
else
|
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
| Line 610... |
Line 610... |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
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else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
end
|
end
|
|
endcase
|
end
|
end
|
`REL8:
|
`REL8:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
|
state <= `SEQ_PC_READ_L; // loads address
|
if (dec_o_p1_optype == `OP_JSR) // bsr
|
if (dec_o_p1_optype == `OP_JSR) // bsr
|
| Line 712... |
Line 713... |
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
default:
|
default:
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_write_post_incdec <= dec_o_ea_wpost;
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
end
|
`SEQ_CWAI_STACK:
|
`SEQ_CWAI_STACK:
|
| Line 816... |
Line 817... |
k_ind_ea <= cpu_data_i;
|
k_ind_ea <= cpu_data_i;
|
state <= `SEQ_IND_DECODE;
|
state <= `SEQ_IND_DECODE;
|
end
|
end
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
begin
|
begin
|
|
k_indirect_loaded <= 1'b0;
|
if (dec_o_ea_ofs8)
|
if (dec_o_ea_ofs8)
|
begin // load 1 byte offset
|
begin // load 1 byte offset
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
end
|
end
|
| Line 837... |
Line 839... |
else
|
else
|
begin // no extra load...
|
begin // no extra load...
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
k_mem_dest <= `MEMDEST_MH; // operand lands in k_memhi/lo
|
next_mem_state <= `SEQ_GRAL_ALU;
|
next_mem_state <= `SEQ_GRAL_ALU;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
|
if (dec_o_ea_indirect)
|
|
k_forced_mem_size <= 1; // to load indirect address
|
end
|
end
|
else
|
else
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
end
|
end
|
end
|
end
|
| Line 859... |
Line 863... |
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
next_mem_state <= `SEQ_GRAL_ALU;
|
next_mem_state <= `SEQ_GRAL_ALU;
|
state <= `SEQ_MEM_READ_H;
|
state <= `SEQ_MEM_READ_H;
|
|
if (dec_o_ea_indirect)
|
|
k_forced_mem_size <= 1; // to load indirect address
|
end
|
end
|
else
|
else
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
end
|
end
|
end
|
end
|
| Line 1010... |
Line 1016... |
end
|
end
|
`SEQ_MEM_READ_H: // reads high byte
|
`SEQ_MEM_READ_H: // reads high byte
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
`INDEXED:
|
|
if (k_indirect_loaded)
|
|
k_cpu_addr <= { k_memhi, k_memlo };
|
|
else
|
|
k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
state <= `SEQ_MEM_READ_H_1;
|
state <= `SEQ_MEM_READ_H_1;
|
else
|
else
|
| Line 1062... |
Line 1072... |
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE, `INHERENT: k_write_dest <= 1; // pull, rts, rti
|
`NONE, `INHERENT: k_write_dest <= 1; // pull, rts, rti
|
endcase
|
endcase
|
if (next_mem_state == `SEQ_LOADPC)
|
if (next_mem_state == `SEQ_LOADPC)
|
k_write_pc <= 1;
|
k_write_pc <= 1;
|
|
case (dec_o_p1_mode)
|
|
`INDEXED: // address loaded, load argument
|
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
state <= next_mem_state;
|
state <= next_mem_state;
|
|
else
|
|
begin
|
|
state <= `SEQ_MEM_READ_H;
|
|
k_indirect_loaded <= 1'b1;
|
|
end
|
|
default:
|
|
state <= next_mem_state;
|
|
endcase
|
end
|
end
|
`SEQ_MEM_WRITE_H: // writes high byte
|
`SEQ_MEM_WRITE_H: // writes high byte
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| Line 1110... |
Line 1131... |
k_new_pc = 16'hffff;
|
k_new_pc = 16'hffff;
|
k_write_tfr = 0;
|
k_write_tfr = 0;
|
k_write_exg = 0;
|
k_write_exg = 0;
|
k_mul_cnt = 0;
|
k_mul_cnt = 0;
|
k_write_dest = 0;
|
k_write_dest = 0;
|
|
k_indirect_loaded = 0;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
