URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [MC6809_cpu.v] - Diff between revs 16 and 17

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Rev 16	Rev 17
Line 105...	Line 105...
`if (cpu_clk)`	`if (cpu_clk)`
`begin`	`begin`
`debug_r[15:0] <= regs_o_pc;`	`debug_r[15:0] <= regs_o_pc;`
`debug_r[23:16] <= k_opcode;`	`debug_r[23:16] <= k_opcode;`
`debug_r[27:24] <= datamux_o_alu_in_left_path_addr;`	`debug_r[27:24] <= datamux_o_alu_in_left_path_addr;`
`debug_r[31:28] <= dec_o_right_path_addr;`	`debug_r[31:28] <= dec_lo_right_path_addr;`
`debug_r[35:32] <= datamux_o_dest_reg_addr;`	`debug_r[35:32] <= datamux_o_dest_reg_addr;`
`debug_r[39:36] <= { 3'b0, k_write_pc }; //regs_o_CCR[3:0];`	`debug_r[39:36] <= { 3'b0, k_write_pc }; //regs_o_CCR[3:0];`
`debug_r[55:40] <= { k_memhi,k_memlo };//k_new_pc;`	`debug_r[55:40] <= { k_memhi,k_memlo };//k_new_pc;`
`debug_r[63:56] <= cpu_data_i;`	`debug_r[63:56] <= cpu_data_i;`
`end`	`end`
Line 168...	Line 168...
`.clk_in(cpu_clk),`	`.clk_in(cpu_clk),`
`.opcode(k_opcode),`	`.opcode(k_opcode),`
`.postbyte0(k_postbyte),`	`.postbyte0(k_postbyte),`
`.page2_valid(k_p2_valid),`	`.page2_valid(k_p2_valid),`
`.page3_valid(k_p3_valid),`	`.page3_valid(k_p3_valid),`

`.path_left_addr_o(dec_o_left_path_addr),`
`.path_right_addr_o(dec_o_right_path_addr),`
`.dest_reg_o(dec_o_dest_reg_addr),`
`.path_left_addr_lo(dec_lo_left_path_addr),`	`.path_left_addr_lo(dec_lo_left_path_addr),`
`.path_right_addr_lo(dec_lo_right_path_addr),`	`.path_right_addr_lo(dec_lo_right_path_addr),`
`.dest_reg_lo(dec_lo_dest_reg_addr),`	`.dest_reg_lo(dec_lo_dest_reg_addr),`
`.write_dest(dec_o_wdest),`	`.write_dest(dec_o_wdest),`
`.source_size(dec_o_source_size),`	`.source_size(dec_o_source_size),`
Line 812...	Line 808...
`end`	`end`
`end`	`end`
`SEQ_JMP_LOAD_PC:	`SEQ_JMP_LOAD_PC:
`begin`	`begin`
state <= `SEQ_FETCH;	state <= `SEQ_FETCH;
	`ifdef CODE_ANALYSIS
	`if (op_JSR)`
	`$display("J JSR [%x]", k_new_pc);`
	`else`
	`if (op_JMP)`
	`$display("J JUMP[%x]", k_new_pc);`
	`else`
	`$display("R JUMP[%x]", k_new_pc);`
	`endif
`end`	`end`
`SEQ_JSR_PUSH:	`SEQ_JSR_PUSH:
`begin`	`begin`
k_pp_active_reg <= `RN_PC; // push PC	k_pp_active_reg <= `RN_PC; // push PC
state <= `SEQ_PUSH_WRITE_L;	state <= `SEQ_PUSH_WRITE_L;
Line 1048...	Line 1053...
state <= `SEQ_MEM_WRITE_L_1;	state <= `SEQ_MEM_WRITE_L_1;
`k_cpu_we <= 1; // write`	`k_cpu_we <= 1; // write`
`end`	`end`
`SEQ_MEM_WRITE_L_1:	`SEQ_MEM_WRITE_L_1:
`begin`	`begin`
`k_write_post_incdec <= dec_o_ea_wpost;`	k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
`state <= next_mem_state;`	`state <= next_mem_state;`
`end`	`end`

`endcase`	`endcase`
`end`	`end`
Line 1070...	Line 1075...
`k_write_dest = 0;`	`k_write_dest = 0;`
`k_indirect_loaded = 0;`	`k_indirect_loaded = 0;`
`end`	`end`
`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [MC6809_cpu.v] - Diff between revs 16 and 17