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https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
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| Rev 9 |
Rev 10 |
| Line 92... |
Line 92... |
output reg carry_out,
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output reg carry_out,
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output reg overflow_out,
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output reg overflow_out,
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output reg half_c_out
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output reg half_c_out
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);
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);
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wire carry;
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assign carry = opcode_in[1] ? carry_in:1'b0;
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always @(*)
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always @(*)
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begin
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begin
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case (opcode_in)
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case (opcode_in[0])
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2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD
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1'b0: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry }; // ADD/ADC
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2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB
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1'b1: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry }; // SUB/SBC
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2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC
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2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC
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endcase
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endcase
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end
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end
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always @(*)
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always @(*)
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begin
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begin
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case (opcode_in)
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case (opcode_in[0])
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2'b00, 2'b10: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) | ((~a_in[7]) & (~b_in[7]) & q_out[7]);
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1'b0: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) | ((~a_in[7]) & (~b_in[7]) & q_out[7]);
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2'b01, 2'b11: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) | ((~a_in[7]) & b_in[7] & q_out[7]);
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1'b1: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) | ((~a_in[7]) & b_in[7] & q_out[7]);
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endcase
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endcase
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end
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end
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always @(*)
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always @(*)
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begin
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begin
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case (opcode_in)
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case (opcode_in[0])
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2'b00, 2'b10: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) | ((~a_in[3]) & (~b_in[3]) & q_out[3]);
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1'b0: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) | ((~a_in[3]) & (~b_in[3]) & q_out[3]);
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2'b01, 2'b11: half_c_out = half_c_in;
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1'b1: half_c_out = half_c_in;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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