Subversion Repositories 6809_6309_compatible_core

                // NEG

                // NEG

assign neg8_r = neg8_w;

assign neg8_r = neg8_w;

assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];

assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];

assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);

assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);

reg [7:0] q8;

reg [7:0] q8;

wire [7:0] logic_q, arith_q, shift_q;

wire [7:0] logic_q, arith_q, shift_q;

wire arith_c, arith_v, arith_h;

wire arith_c, arith_v, arith_h;

wire shift_c, shift_v;

wire shift_c, shift_v;

        end

        end

*/

*/

always @(*)

always @(*)

        begin

        begin

                q_out[7:0] = q8; //regq8;

                q_out[7:0] = q8; //regq8;

                CCRo = { CCR[7:6], h8, CCR[4], q8[7], (q8 == 8'h0), v8, c8 };

                CCRo = { CCR[7:6], h8, CCR[4], q8[7], (q8 == 8'h0), v8, c8 };

        end

        end

initial

initial

        begin

        begin

reg c16, n16, v16, z16;

reg c16, n16, v16, z16;

reg [15:0] q16;

reg [15:0] q16;

wire [15:0] arith_q;

wire [15:0] arith_q;

arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);

arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);

always @(*)

always @(*)

        begin

        begin

                                        q16 = a_in[15:0];

                                        q16 = a_in[15:0];

                                end

                                end

                endcase

                endcase

        end

        end

reg reg_n_in, reg_z_in;

reg reg_n_in, reg_z_in;

/* register before second mux */

/* register before second mux */

always @(posedge clk_in)

always @(posedge clk_in)

        begin

        begin

                reg_n_in <= n_in;

                reg_n_in <= n_in;

                reg_z_in <= z_in;

                reg_z_in <= z_in;

        end

        end

/* Negative & zero flags */

/* Negative & zero flags */