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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Diff between revs 2 and 4

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Rev 2	Rev 4
Line 364...	Line 364...
`end`	`end`
`SEXT: // sign extend	`SEXT: // sign extend
`begin`	`begin`
`q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };`	`q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };`
`end`	`end`
	`LEA:
	`begin`
	`q16 = a_in[15:0];`
	`end`
`endcase`	`endcase`
`end`	`end`

`reg [7:0] regq8;`	`reg [7:0] regq8;`
`reg [15:0] regq16;`	`reg [15:0] regq16;`
Line 463...	Line 467...
`SEXT: // sign extend	`SEXT: // sign extend
`begin`	`begin`
`n16 = reg_n_in;`	`n16 = reg_n_in;`
`z16 = reg_z_in;`	`z16 = reg_z_in;`
`end`	`end`
	`LEA: // only Z will be affected
	`begin`
	`n16 = reg_n_in;`
	`end`
`endcase`	`endcase`
`end`	`end`


`always @(*)`	`always @(*)`
Line 474...	Line 482...
`q_out[15:8] = regq16[15:8];`	`q_out[15:8] = regq16[15:8];`
`if (sz_in)`	`if (sz_in)`
`q_out[7:0] = regq16[7:0];`	`q_out[7:0] = regq16[7:0];`
`else`	`else`
`q_out[7:0] = regq8;`	`q_out[7:0] = regq8;`

`case (opcode_in)`	`case (opcode_in)`
`ORCC:	`ORCC:
`CCRo = CCR \| b_in[7:0];`	`CCRo = CCR \| b_in[7:0];`
`ANDCC:	`ANDCC:
`CCRo = CCR & b_in[7:0];`	`CCRo = CCR & b_in[7:0];`

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