| Line 10... |
Line 10... |
input wire cpu_clk,
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input wire cpu_clk,
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output reg [3:0] path_left_addr_o,
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output wire [3:0] path_left_addr_o,
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output reg [3:0] path_right_addr_o,
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output wire [3:0] path_right_addr_o,
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output reg [3:0] dest_reg_o,
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output wire [3:0] dest_reg_o,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] dest_reg_lo,
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output wire write_dest,
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output wire write_dest,
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output wire source_size,
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output wire source_size,
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output wire result_size
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output wire result_size
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);
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);
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reg [3:0] path_left_addr, path_right_addr, dest_reg;
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reg [3:0] path_left_addr, path_right_addr, dest_reg;
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// for registers, memory writes are handled differently
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// for registers, memory writes are handled differently
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assign write_dest = (dest_reg != `RN_INV);
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assign write_dest = (dest_reg != `RN_INV);
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assign source_size = (path_left_addr < `RN_ACCA);
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assign source_size = (path_left_addr < `RN_ACCA);
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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assign path_right_addr_o = path_right_addr;
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assign path_left_addr_o = path_left_addr;
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assign dest_reg_o = dest_reg;
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always @(opcode, postbyte0, page2_valid, page3_valid)
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always @(opcode, postbyte0, page2_valid, page3_valid)
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begin
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begin
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path_left_addr = `RN_INV;
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path_left_addr = `RN_INV;
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path_right_addr = `RN_INV;
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path_right_addr = `RN_INV;
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dest_reg = `RN_INV;
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dest_reg = `RN_INV;
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| Line 80... |
Line 89... |
8'h33: dest_reg = `RN_U;
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8'h33: dest_reg = `RN_U;
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8'h39: dest_reg = `RN_PC; // rts
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8'h39: dest_reg = `RN_PC; // rts
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8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
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8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
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8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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8'h0x, 8'h7x: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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8'h0x, 8'h6x, 8'h7x:
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8'h6x:
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case (opcode[3:0])
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case (opcode[3:0])
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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endcase
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8'h8x, 8'h9x, 8'hax, 8'hbx:
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8'h8x, 8'h9x, 8'hax, 8'hbx:
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| Line 122... |
Line 130... |
8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
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8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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endcase
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endcase
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end
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end
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// latched versions are used to fetch regsiters
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// not-latched version in the decoder
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always @(posedge cpu_clk)
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always @(posedge cpu_clk)
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begin
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begin
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path_right_addr_o <= path_right_addr;
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path_right_addr_lo <= path_right_addr;
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path_left_addr_o <= path_left_addr;
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path_left_addr_lo <= path_left_addr;
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dest_reg_o <= dest_reg;
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dest_reg_lo <= dest_reg;
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end
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end
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endmodule
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endmodule
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/* Decodes module and addressing mode for page 1 opcodes */
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/* Decodes module and addressing mode for page 1 opcodes */
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module decode_op(
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module decode_op(
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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| Line 327... |
Line 338... |
8'h04, 8'b01xx_0100: alu_opcode = `LSR;
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8'h04, 8'b01xx_0100: alu_opcode = `LSR;
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8'h06, 8'b01xx_0110: alu_opcode = `ROR;
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8'h06, 8'b01xx_0110: alu_opcode = `ROR;
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8'h07, 8'b01xx_0111: alu_opcode = `ASR;
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8'h07, 8'b01xx_0111: alu_opcode = `ASR;
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8'h08, 8'b01xx_1000: alu_opcode = `LSL;
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8'h08, 8'b01xx_1000: alu_opcode = `LSL;
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8'h09, 8'b01xx_1001: alu_opcode = `ROL;
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8'h09, 8'b01xx_1001: alu_opcode = `ROL;
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8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_MINUS1; end // dec
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8'h0a, 8'b01xx_1010: begin alu_opcode = `SUB; dec_alu_right_path_mod = `MOD_ONE; end // dec
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8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
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8'h0c, 8'b01xx_1100: begin alu_opcode = `ADD; dec_alu_right_path_mod = `MOD_ONE; end // inc
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8'h0d, 8'b01xx_1101: alu_opcode = `AND;
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8'h0d, 8'b01xx_1101: alu_opcode = `AND;
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8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
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8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
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8'h19: alu_opcode = `DAA;
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8'h19: alu_opcode = `DAA;
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