| Line 157... |
Line 157... |
input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output reg [2:0] mode,
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output reg [2:0] mode,
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output reg [2:0] optype,
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output reg [2:0] optype,
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output reg op_SYNC,
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output reg op_EXG,
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output reg op_TFR,
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output reg op_RTS,
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output reg op_RTI,
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output reg op_CWAI,
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output reg op_MUL,
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output reg op_SWI,
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output reg op_PUSH,
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output reg op_PULL,
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output reg op_LEA,
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output reg op_JMP,
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output reg op_JSR,
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output reg use_s
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output reg use_s
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);
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);
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wire [3:0] oplo;
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wire [3:0] oplo;
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reg size;
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reg size;
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| Line 168... |
Line 181... |
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always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
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always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
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begin
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begin
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//dsize = `DSZ_8; // data operand size
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//dsize = `DSZ_8; // data operand size
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//msize = `MSZ_8; // memory operand size
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//msize = `MSZ_8; // memory operand size
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optype = `OP_NONE;
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use_s = 1;
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use_s = 1;
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mode = `NONE;
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mode = `NONE;
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size = 0;
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size = 0;
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op_SYNC = 0;
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op_EXG = 0;
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op_TFR = 0;
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op_RTS = 0;
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op_RTI = 0;
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op_CWAI = 0;
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op_MUL = 0;
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op_SWI = 0;
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op_PUSH = 0;
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op_PULL = 0;
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op_LEA = 0;
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op_JMP = 0;
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op_JSR = 0;
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// Addressing mode
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// Addressing mode
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casex(opcode)
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casex(opcode)
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8'h0x: begin mode = `DIRECT; end
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8'h0x: begin mode = `DIRECT; end
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//8'h0e: begin optype = `OP_JMP; end
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//8'h0e: begin optype = `OP_JMP; end
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8'h12, 8'h13, 8'h19: mode = `INHERENT;
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8'h12, 8'h13, 8'h19: mode = `INHERENT;
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8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
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8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
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8'h16: mode = `REL16;
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8'h16: mode = `REL16;
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8'h17: begin mode = `REL16; optype = `OP_JSR; end
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8'h17: begin mode = `REL16; op_JSR = 1; end
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8'h1a, 8'h1c, 8'h1d, 8'h1e, 8'h1f: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
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8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
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8'h1e: op_EXG = 1;
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8'h1f: op_TFR = 1;
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8'h2x: mode = `REL8;
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8'h2x: mode = `REL8;
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8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; optype = `OP_LEA; end
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8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
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8'h34: begin optype = `OP_PUSH; mode = `NONE; end
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8'h34: op_PUSH = 1;
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8'h35: begin optype = `OP_PULL; mode = `NONE; end
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8'h35: op_PULL = 1;
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8'h36: begin optype = `OP_PUSH; mode = `NONE; use_s = 0; end
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8'h36: begin op_PUSH = 1; use_s = 0; end
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8'h37: begin optype = `OP_PULL; mode = `NONE; use_s = 0; end
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8'h37: begin op_PULL = 1; use_s = 0; end
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8'h38, 8'h3e: mode = `NONE;
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8'h38, 8'h3e: mode = `NONE;
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// don't change to inh because SEQ_MEM_READ_x would not use register S as address
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// don't change to inh because SEQ_MEM_READ_x would not use register S as address
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8'h39, 8'h3b: begin mode = `NONE; optype = `OP_RTS; end
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8'h39: begin op_RTS = 1; mode = `INHERENT; end
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8'h3a, 8'h3c, 8'h3d, 8'h3f: mode = `INHERENT;
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8'h3b: begin op_RTI = 1; mode = `INHERENT; end
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8'h3a, 8'h3c: mode = `INHERENT;
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8'h3d: begin op_MUL = 1; mode = `INHERENT; end
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8'h3f: begin op_SWI = 1; mode = `INHERENT; end
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8'h4x: begin mode = `INHERENT; end
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8'h4x: begin mode = `INHERENT; end
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8'h5x: begin mode = `INHERENT; end
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8'h5x: begin mode = `INHERENT; end
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8'h6x: begin mode = `INDEXED; end
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8'h6x: begin mode = `INDEXED; end
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//8'h6e: begin optype = `OP_JMP; end
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//8'h6e: begin optype = `OP_JMP; end
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8'h7x: begin mode = `EXTENDED; end
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8'h7x: begin mode = `EXTENDED; end
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| Line 220... |
Line 248... |
8'hax, 8'hex: begin mode = `INDEXED; end
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8'hax, 8'hex: begin mode = `INDEXED; end
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8'hbx, 8'hfx: begin mode = `EXTENDED; end
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8'hbx, 8'hfx: begin mode = `EXTENDED; end
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endcase
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endcase
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// Opcode type
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// Opcode type
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casex(opcode)
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casex(opcode)
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8'b1xxx0110: optype = `OP_LD;
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8'h0e, 8'h6e, 8'h7e: op_JMP = 1;
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8'h0e, 8'h6e, 8'h7e: optype = `OP_JMP;
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8'b10xx1101: op_JSR = 1; // bsr & jsr
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8'b11xx1100: optype = `OP_LD; // LDD
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8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
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8'b1xxx1110: optype = `OP_LD; // LDX, LDU
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//8'b1xxx1111, 8'b11xx1101: optype = `OP_ST;
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endcase
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endcase
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if (page2_valid == 1'b1)
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if (page2_valid == 1'b1)
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begin
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begin
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casex(postbyte0)
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casex(postbyte0)
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8'h2x: mode = `REL16;
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8'h2x: mode = `REL16;
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8'h3f: mode = `INHERENT;
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8'h3f: op_SWI = 1;
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8'h83: begin mode = `IMMEDIATE; size = 1; end
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8'h83: begin mode = `IMMEDIATE; size = 1; end
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
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//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
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//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
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8'h8e: begin mode = `IMMEDIATE; size = 1; end
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8'h8e: begin mode = `IMMEDIATE; size = 1; end
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| Line 248... |
Line 272... |
casex( postbyte0)
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casex( postbyte0)
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8'h9x, 8'hdx: mode = `DIRECT;
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8'h9x, 8'hdx: mode = `DIRECT;
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8'hax, 8'hex: mode = `INDEXED;
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8'hax, 8'hex: mode = `INDEXED;
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8'hbx, 8'hfx: mode = `EXTENDED;
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8'hbx, 8'hfx: mode = `EXTENDED;
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endcase
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endcase
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casex( postbyte0)
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8'b1xxx1110: optype = `OP_LD; // LDY, LDS
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//8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST; // STY, STS
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endcase
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end
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end
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if (page3_valid == 1'b1)
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if (page3_valid == 1'b1)
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begin
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begin
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casex(postbyte0)
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casex(postbyte0)
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8'h3f: mode = `INHERENT;
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8'h3f: op_SWI = 1;
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8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
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8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
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//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
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8'h8c: begin mode = `IMMEDIATE; size = 1; end
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//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
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//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
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8'h8e: begin mode = `IMMEDIATE; size = 1; end
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8'h8e: begin mode = `IMMEDIATE; size = 1; end
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