| Line 116... |
Line 116... |
default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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endcase
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8'hcx, 8'hdx, 8'hex, 8'hfx:
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8'hcx, 8'hdx, 8'hex, 8'hfx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // addd
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // stb
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4'hd: begin path_left_addr = `RN_ACCD; end // LDD
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4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // ldd
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
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4'hd: begin path_left_addr = `RN_ACCD; dest_reg = `RN_MEM16; end // STD
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4'he: begin dest_reg = `RN_U; end // LDU
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4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
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4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
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default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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endcase
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endcase
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endcase
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endcase
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casex (opcode) // right arm
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casex (opcode) // right arm
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// 8x and Cx
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// 8x and Cx
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8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
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8'b1x00_000x, 8'b1x00_0010, // sub, cmp, scb
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8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
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8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
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8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
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// 83, C3, 8C, CC, 8E, CE
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8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
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// 9, A, B, D, E, F
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// 9, A, B, D, E, F
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8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
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8'b1x01_000x, 8'b1x01_0010, // x0, x1, x2: sub cmp, scb
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8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
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8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx,
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8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_000x, 8'b1x1x_0010,
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8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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// 9x, Ax, Bx, Dx, Ex, Fx
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8'h93, 8'ha3, 8'hb3, // subd
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8'hd3, 8'he3, 8'hf3, // addd
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8'h9c, 8'hac, 8'hbc, // cmpx
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8'hdc, 8'hec, 8'hfc, // ldd
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//8'hdd, 8'hed, 8'hfd, // std
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8'h9e, 8'hae, 8'hbe, // ldx
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8'hde, 8'hee, 8'hfe, // ldu
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//8'h9f, 8'haf, 8'hbf, // stx
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8'hdf, 8'hef, 8'hff: path_right_addr = `RN_MEM16;// stu
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endcase
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endcase
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end
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end
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// latched versions are used to fetch regsiters
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// latched versions are used to fetch regsiters
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// not-latched version in the decoder
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// not-latched version in the decoder
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always @(posedge cpu_clk)
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always @(posedge cpu_clk)
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| Line 358... |
Line 368... |
8'b1xxx_1001: alu_opcode = `ADC;
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8'b1xxx_1001: alu_opcode = `ADC;
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8'b1xxx_1010: alu_opcode = `OR;
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8'b1xxx_1010: alu_opcode = `OR;
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8'b1xxx_1011: alu_opcode = `ADD;
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8'b1xxx_1011: alu_opcode = `ADD;
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8'b10xx_1100: alu_opcode = `SUB; // CMP
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8'b10xx_1100: alu_opcode = `SUB; // CMP
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8'b11xx_1100: alu_opcode = `LD;
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8'b11xx_1100: alu_opcode = `LD;
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8'b11xx_1101: alu_opcode = `LD;
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8'b11xx_1101: alu_opcode = `ST;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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8'b1xxx_1111: alu_opcode = `ST;
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8'h00, 8'b01xx_0000: alu_opcode = `NEG;
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8'h00, 8'b01xx_0000: alu_opcode = `NEG;
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8'h03, 8'b01xx_0011: alu_opcode = `COM;
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8'h03, 8'b01xx_0011: alu_opcode = `COM;
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