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/*
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/*
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* Signals which registers have to be read/written for the current opcode
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* Decodes an opcode
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*
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*
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*
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* All decoders in one module
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*
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*
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*/
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*/
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`include "defs.v"
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`include "defs.v"
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module decoders(
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module decoders(
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output wire [3:0] path_left_addr_o,
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output wire [3:0] path_right_addr_o,
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output wire [3:0] dest_reg_o,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] dest_reg_lo,
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output reg [3:0] dest_reg_lo,
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output wire write_dest,
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output wire write_dest,
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output wire source_size,
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output wire source_size,
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output wire [4:0] alu_opcode,
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output wire [4:0] alu_opcode,
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output wire dest_flags_o
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output wire dest_flags_o
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);
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);
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reg [3:0] lr, rr, dr;
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reg [3:0] lr, rr, dr; // left, right and destination register addresses
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reg [1:0] lm, rm, dm;
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reg [1:0] lm, rm, dm; // left, right and destination memory sizes
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reg ss, sz, p2, p3;
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reg ss, sz, p2, p3; // S or *U, 16 or *8, page 2, page 3
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reg [2:0] mo;
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reg [2:0] mo; // Addressing Mode
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reg [4:0] aop;
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reg [4:0] aop; // ALU opcode
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assign write_dest = (dr != `RN_INV);
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assign write_dest = (dr != `RN_INV);
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assign source_size = (lr < `RN_ACCA) | sz | (rm == `MT_WORD);
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assign source_size = (lr < `RN_ACCA) | sz | (rm == `MT_WORD);
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// result size is used to determine the size of the argument
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// result size is used to determine the size of the argument
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// to load, compare has no result, thus the source is used instead,
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// to load, compare has no result, thus the source is used instead,
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// why do we need the result size ?... because of tfr&exg
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// why do we need the result size ?... because of tfr&exg
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assign result_size = (dr == `RN_INV) ? (lr < `RN_ACCA):
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assign result_size = (dr == `RN_INV) ? (lr < `RN_ACCA):
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(dr < `RN_ACCA) ? 1:0;
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(dr < `RN_ACCA) ? 1:0;
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assign path_right_addr_o = rr;
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assign path_left_addr_o = lr;
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assign dest_reg_o = dr;
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// for registers, memory writes are handled differently
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// for registers, memory writes are handled differently
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assign operand_read_o = (lm != `MT_NONE) | (rm != `MT_NONE);
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assign operand_read_o = (lm != `MT_NONE) | (rm != `MT_NONE);
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assign operand_write_o = dm != `MT_NONE;
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assign operand_write_o = dm != `MT_NONE;
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assign path_left_memtype_o = lm;
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assign path_left_memtype_o = lm;
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wire [7:0] op = page2_valid ? postbyte0:opcode;
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wire [7:0] op = page2_valid ? postbyte0:opcode;
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always @(*)
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always @(*)
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begin
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begin
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cond_taken = 1'b0;
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cond_taken = 1'b0;
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if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D) ||
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if ((opcode == 8'h16) || (opcode == 8'h17) || (opcode == 8'h8D) ||
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(op == 8'h0e) || (op == 8'h6e) || (op == 8'h7e)) // jmp
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(opcode == 8'h0e) || (opcode == 8'h6e) || (opcode == 8'h7e)) // jmp
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cond_taken = 1'b1; // LBRA/LBSR, BSR
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cond_taken = 1'b1; // LBRA/LBSR, BSR
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if (op[7:4] == 4'h2)
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if (op[7:4] == 4'h2)
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case (op[3:0])
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case (op[3:0])
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4'h0: cond_taken = 1'b1; // BRA
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4'h0: cond_taken = 1'b1; // BRA
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4'h1: cond_taken = 0; // BRN
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4'h1: cond_taken = 0; // BRN
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