| Line 12... |
Line 12... |
input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output reg [3:0] path_left_addr,
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output reg [3:0] path_left_addr,
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output reg [3:0] path_right_addr,
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output reg [3:0] path_right_addr,
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output reg [3:0] dest_reg,
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output reg [3:0] dest_reg,
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output wire write_dest_8,
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output wire write_dest,
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output wire write_dest_16,
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output wire source_size,
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output wire result_size
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output wire result_size
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);
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);
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// for registers, memory writes are handled differently
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// for registers, memory writes are handled differently
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assign write_dest_8 = ((dest_reg >= `RN_ACCA) && (dest_reg <= `RN_DP)) ? 1:0;
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assign write_dest = (dest_reg != `RN_INV);
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assign write_dest_16 = (dest_reg < `RN_IMM16) ? 1:0;
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assign source_size = (path_left_addr < `RN_ACCA);
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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always @(opcode, postbyte0, page2_valid, page3_valid)
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always @(opcode, postbyte0, page2_valid, page3_valid)
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begin
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begin
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path_left_addr = `RN_INV;
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path_left_addr = `RN_INV;
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path_right_addr = `RN_INV;
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path_right_addr = `RN_INV;
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dest_reg = `RN_INV;
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dest_reg = `RN_INV;
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if (page2_valid)
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if (page2_valid | page3_valid)
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begin
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begin
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casex(postbyte0)
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD;
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY;
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY;
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8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
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8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY;
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8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
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8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
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endcase
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endcase
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casex (postbyte0) // right arm
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casex (postbyte0) // right arm
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8'h83, 8'h8c, 8'h8e, 8'h8f: path_right_addr = `RN_IMM16;
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8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16;
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8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16;
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8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
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endcase
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endcase
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casex(postbyte0) // dest
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // only flags
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu/cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // only flags
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy/cmps
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY;
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY;
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8'h8f, 8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16;
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8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
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8'h8f, 8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
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8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STS
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endcase
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end
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if (page3_valid)
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begin
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
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endcase
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casex (postbyte0) // right arm
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8'h83, 8'h8c: path_right_addr = `RN_IMM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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endcase
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
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endcase
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endcase
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end
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end
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// destination
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// destination
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casex(opcode)
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casex(opcode)
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8'h30: dest_reg = `RN_IX;
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8'h30: dest_reg = `RN_IX;
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| Line 66... |
Line 85... |
4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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endcase
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8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
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8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1: path_left_addr = `RN_ACCA; // CMP
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
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4'hc, 4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hd: begin end // nothing active, jsr
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4'hd: begin end // nothing active, jsr
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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endcase
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8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
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8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1: path_left_addr = `RN_ACCB; // CMP
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hd: begin path_left_addr = `RN_ACCD; end
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4'hd: begin path_left_addr = `RN_ACCD; end
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| Line 309... |
Line 331... |
8'h19: alu_opcode = `DAA;
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8'h19: alu_opcode = `DAA;
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8'h1a: alu_opcode = `ORCC;
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8'h1a: alu_opcode = `ORCC;
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8'h1c: alu_opcode = `ANDCC;
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8'h1c: alu_opcode = `ANDCC;
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8'h1d: alu_opcode = `SEXT;
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8'h1d: alu_opcode = `SEXT;
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8'h1e: alu_opcode = `EXG;
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8'h1e: alu_opcode = `EXG;
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8'b0011_000x: alu_opcode = `LEA;
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8'h3d: alu_opcode = `MUL;
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8'h3d: alu_opcode = `MUL;
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endcase
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endcase
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if (page2_valid)
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if (page2_valid)
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casex (postbyte0)
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casex (postbyte0)
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8'b10xx_0011,
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8'b10xx_0011,
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