URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Diff between revs 12 and 14

Rev 12	Rev 14
Line 141...	Line 141...
`define MSZ_16 2'h2	`define MSZ_16 2'h2
`// Data transfer size, to save to register, used for data from memory and to save results to memory/registers`	`// Data transfer size, to save to register, used for data from memory and to save results to memory/registers`
`define DSZ_0 2'h0	`define DSZ_0 2'h0
`define DSZ_8 2'h1	`define DSZ_8 2'h1
`define DSZ_16 2'h2	`define DSZ_16 2'h2
	`/*`
`define OP_NONE 3'h0	`define OP_NONE 3'h0
`define OP_PUSH 3'h1	`define OP_PUSH 3'h1
`define OP_PULL 3'h2	`define OP_PULL 3'h2
`define OP_RTS 3'h3	`define OP_RTS 3'h3
`define OP_JSR 3'h4	`define OP_JSR 3'h4
`define OP_JMP 3'h5	`define OP_JMP 3'h5
`define OP_LD 3'h6	`define OP_LEA 3'h6
`define OP_LEA 3'h7	`define OP_X 3'h7
	`*/`

`/* alu decoder right path modifier */`	`/* alu decoder right path modifier */`
`define MOD_DEFAULT 2'h0	`define MOD_DEFAULT 2'h0
`define MOD_ONE 2'h1	`define MOD_ONE 2'h1
`define MOD_ZERO 2'h2	`define MOD_ZERO 2'h2