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Line 5... |
`define RN_IX 4'h1
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`define RN_IX 4'h1
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`define RN_IY 4'h2
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`define RN_IY 4'h2
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`define RN_U 4'h3
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`define RN_U 4'h3
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`define RN_S 4'h4
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`define RN_S 4'h4
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`define RN_PC 4'h5
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`define RN_PC 4'h5
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`define RN_MEM16 4'h6
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//`define RN_MEM16 4'h6
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`define RN_IMM16 4'h7
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//`define RN_IMM16 4'h7
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`define RN_ACCA 4'h8
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`define RN_ACCA 4'h8
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`define RN_ACCB 4'h9
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`define RN_ACCB 4'h9
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`define RN_CC 4'ha
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`define RN_CC 4'ha
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`define RN_DP 4'hb
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`define RN_DP 4'hb
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`define RN_MEM8 4'hc
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//`define RN_MEM8 4'hc
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`define RN_IMM8 4'hd
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//`define RN_IMM8 4'hd
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`define RN_INV 4'hf
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`define RN_INV 4'hf
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// opcodes that need an ALU result
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// opcodes that need an ALU result
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`define NOP 5'b00000
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`define NOP 5'b00000
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`define INC 5'b11000 // encoding of least 2 bits must be like ADD/SUB
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`define INC 5'b11000 // encoding of least 2 bits must be like ADD/SUB
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`define DEC 5'b11001
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`define DEC 5'b11001
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`define DAA 5'b11010
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`define DAA 5'b11010
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`define MUL 5'b11011
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`define MUL 5'b11011
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`define LEA 5'b11100
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`define LEA 5'b11100
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`define CLR 5'b11101
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`define TST 5'b11110
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/* Sequencer states */
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/* Sequencer states */
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`define SEQ_COLDRESET 'h00
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`define SEQ_COLDRESET 'h00
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`define SEQ_NMI 'h01
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`define SEQ_NMI 'h01
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| Line 63... |
Line 65... |
`define SEQ_FETCH_3 'h0c
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`define SEQ_FETCH_3 'h0c
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`define SEQ_FETCH_4 'h0d
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`define SEQ_FETCH_4 'h0d
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`define SEQ_FETCH_5 'h0e
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`define SEQ_FETCH_5 'h0e
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`define SEQ_DECODE 'h0f
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`define SEQ_DECODE 'h0f
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`define SEQ_DECODE_P23 'h10
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`define SEQ_DECODE_P23 'h10 // x
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`define SEQ_GRAL_ALU 'h11
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`define SEQ_GRAL_ALU 'h11
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`define SEQ_GRAL_WBACK 'h12
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`define SEQ_GRAL_WBACK 'h12
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`define SEQ_CWAI_STACK 'h13 // stacks registers
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`define SEQ_CWAI_STACK 'h13 // stacks registers
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`define SEQ_CWAI_WAIT 'h14 // waits for an interrupt
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`define SEQ_CWAI_WAIT 'h14 // waits for an interrupt
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Line 82... |
`define SEQ_IND_DECODE_OFS 'h1a // used to load 8 or 16 bits offset
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`define SEQ_IND_DECODE_OFS 'h1a // used to load 8 or 16 bits offset
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`define SEQ_JMP_LOAD_PC 'h1b
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`define SEQ_JMP_LOAD_PC 'h1b
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`define SEQ_JSR_PUSH 'h1c
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`define SEQ_JSR_PUSH 'h1c
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`define SEQ_JSR_PUSH_L 'h1d
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`define SEQ_JSR_PUSH_L 'h1d // x
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`define SEQ_RTS_POP_L 'h1e
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`define SEQ_RTS_POP_L 'h1e // x
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`define SEQ_RTS_POP_H 'h1f
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`define SEQ_RTS_POP_H 'h1f // x
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`define SEQ_PREPUSH 'h20
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`define SEQ_PREPUSH 'h20
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`define SEQ_PREPULL 'h21
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`define SEQ_PREPULL 'h21
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`define SEQ_PUSH_WRITE_L 'h22
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`define SEQ_PUSH_WRITE_L 'h22
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`define SEQ_PUSH_WRITE_L_1 'h23
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`define SEQ_PUSH_WRITE_L_1 'h23
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Line 143... |
`define MSZ_16 2'h2
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`define MSZ_16 2'h2
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// Data transfer size, to save to register, used for data from memory and to save results to memory/registers
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// Data transfer size, to save to register, used for data from memory and to save results to memory/registers
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`define DSZ_0 2'h0
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`define DSZ_0 2'h0
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`define DSZ_8 2'h1
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`define DSZ_8 2'h1
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`define DSZ_16 2'h2
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`define DSZ_16 2'h2
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/*
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/* Memory access type for input/output operands */
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`define OP_NONE 3'h0
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`define MT_NONE 3'h0
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`define OP_PUSH 3'h1
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`define MT_BYTE 3'h1
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`define OP_PULL 3'h2
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`define MT_WORD 3'h2
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`define OP_RTS 3'h3
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`define MT_QUAD 3'h3
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`define OP_JSR 3'h4
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`define OP_JMP 3'h5
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`define OP_LEA 3'h6
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`define OP_X 3'h7
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*/
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/* alu decoder right path modifier */
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/* alu decoder right path modifier */
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`define MOD_DEFAULT 2'h0
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`define MOD_DEFAULT 2'h0
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`define MOD_ONE 2'h1
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`define MOD_ONE 2'h1
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`define MOD_ZERO 2'h2
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`define MOD_ZERO 2'h2
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`define MOD_MINUS1 2'h3
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`define MOD_MINUS1 2'h3
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// Memory source address
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`define MEMDEST_PC 2'h0
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`define MEMDEST_PC 1'h0
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`define MEMDEST_MH 2'h1
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`define MEMDEST_MH 1'h1
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`define MEMDEST_AH 2'h2
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`define MEMDEST_I16 2'h3
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