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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Diff between revs 2 and 4

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Rev 2 Rev 4
Line 35... Line 35...
`define T168H  5'b01101
`define T168H  5'b01101
`define SEXT   5'b01110
`define SEXT   5'b01110
`define EXG    5'b01111
`define EXG    5'b01111
 
 
`define NEG    5'b10000
`define NEG    5'b10000
`define COM    5'b10011
`define COM    5'b10001
`define LSR    5'b10100
`define LSR    5'b10010
`define ROR    5'b10110
`define ROR    5'b10011
`define ASR    5'b10111
`define ASR    5'b10100
`define LSL    5'b11000
`define LSL    5'b10101
`define ROL    5'b11001
`define ROL    5'b10110
`define ORCC   5'b11010
`define ORCC   5'b10111
`define ANDCC  5'b11011
`define ANDCC  5'b11000
 
`define DAA    5'b11001
`define DAA    5'b11100
`define MUL    5'b11010
`define MUL    5'b11101
`define T816   5'b11011
`define T816   5'b11110
`define LEA    5'b11100
 
 
/* Sequencer states */
/* Sequencer states */
 
 
`define SEQ_COLDRESET           'h00
`define SEQ_COLDRESET           'h00
`define SEQ_NMI                         'h01
`define SEQ_NMI                         'h01

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