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https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
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Rev 4 |
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input wire [3:0] path_left_addr,
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input wire [3:0] path_left_addr,
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input wire [3:0] path_right_addr,
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input wire [3:0] path_right_addr,
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input wire [3:0] write_reg_addr,
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input wire [3:0] write_reg_addr,
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input wire [7:0] eapostbyte, // effective address post byte
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input wire [7:0] eapostbyte, // effective address post byte
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input wire [15:0] offset16, // up to 16 bit offset for effective address calculation
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input wire [15:0] offset16, // up to 16 bit offset for effective address calculation
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input wire write_reg_8,
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input wire write_reg,
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input wire write_reg_16,
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input wire write_pull_reg,
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input wire write_post,
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input wire write_post,
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input wire write_pc,
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input wire write_pc,
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input wire inc_pc,
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input wire inc_pc,
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input wire inc_su, /* increments S or U */
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input wire inc_su, /* increments S or U */
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input wire dec_su, /* decrements s or u */
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input wire dec_su, /* decrements s or u */
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endcase
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endcase
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end
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end
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always @(posedge clk_in)
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always @(posedge clk_in)
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begin
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begin
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if (write_reg_8 | write_reg_16 | write_pull_reg)
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if (write_reg)
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case (write_reg_addr)
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case (write_reg_addr)
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0: `ACCD <= data_w;
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0: `ACCD <= data_w;
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1: IX <= data_w;
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1: IX <= data_w;
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2: IY <= data_w;
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2: IY <= data_w;
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3: SU <= data_w;
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3: SU <= data_w;
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