| Line 1... |
Line 1... |
$date
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$date
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Mon Jan 6 06:54:14 2014
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Sun Jun 22 08:16:49 2014
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$end
|
$end
|
$version
|
$version
|
Icarus Verilog
|
Icarus Verilog
|
$end
|
$end
|
$timescale
|
$timescale
|
| Line 22... |
Line 22... |
$var wire 1 * cpu_firq_n $end
|
$var wire 1 * cpu_firq_n $end
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$var wire 1 + cpu_irq_n $end
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$var wire 1 + cpu_irq_n $end
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$var wire 1 , cpu_nmi_n $end
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$var wire 1 , cpu_nmi_n $end
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$var wire 1 ) cpu_reset $end
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$var wire 1 ) cpu_reset $end
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$var wire 6 - cpu_state_o [5:0] $end
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$var wire 6 - cpu_state_o [5:0] $end
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$var wire 1 . k_firq_req $end
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$var wire 1 . debug_clk $end
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$var wire 1 / k_irq_req $end
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$var wire 1 / debug_data_o $end
|
$var wire 1 0 k_nmi_req $end
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$var wire 1 0 k_firq_req $end
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$var wire 1 1 k_reset $end
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$var wire 1 1 k_irq_req $end
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$var wire 16 2 regs_o_su [15:0] $end
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$var wire 1 2 k_nmi_req $end
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$var wire 16 3 regs_o_right_path_data [15:0] $end
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$var wire 1 3 k_reset $end
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$var wire 16 4 regs_o_pc [15:0] $end
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$var wire 16 4 regs_o_su [15:0] $end
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$var wire 16 5 regs_o_left_path_data [15:0] $end
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$var wire 16 5 regs_o_right_path_data [15:0] $end
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$var wire 16 6 regs_o_eamem_addr [15:0] $end
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$var wire 16 6 regs_o_pc [15:0] $end
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$var wire 8 7 regs_o_dp [7:0] $end
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$var wire 16 7 regs_o_left_path_data [15:0] $end
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$var wire 8 8 regs_o_CCR [7:0] $end
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$var wire 16 8 regs_o_eamem_addr [15:0] $end
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$var wire 1 9 dec_o_write_flags $end
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$var wire 8 9 regs_o_dp [7:0] $end
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$var wire 1 : dec_o_wdest $end
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$var wire 8 : regs_o_CCR [7:0] $end
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$var wire 1 ; dec_o_use_s $end
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$var wire 1 ; dec_o_write_flags $end
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$var wire 1 < dec_o_source_size $end
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$var wire 1 < dec_o_wdest $end
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$var wire 2 = dec_o_right_path_mod [1:0] $end
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$var wire 1 = dec_o_use_s $end
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$var wire 4 > dec_o_right_path_addr [3:0] $end
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$var wire 1 > dec_o_source_size $end
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$var wire 3 ? dec_o_p1_optype [2:0] $end
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$var wire 2 ? dec_o_right_path_mod [1:0] $end
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$var wire 3 @ dec_o_p1_mode [2:0] $end
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$var wire 4 @ dec_o_right_path_addr [3:0] $end
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$var wire 4 A dec_o_left_path_addr [3:0] $end
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$var wire 3 A dec_o_p1_optype [2:0] $end
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$var wire 1 B dec_o_ea_wpost $end
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$var wire 3 B dec_o_p1_mode [2:0] $end
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$var wire 1 C dec_o_ea_ofs8 $end
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$var wire 4 C dec_o_left_path_addr [3:0] $end
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$var wire 1 D dec_o_ea_ofs16 $end
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$var wire 1 D dec_o_ea_wpost $end
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$var wire 1 E dec_o_ea_ofs0 $end
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$var wire 1 E dec_o_ea_ofs8 $end
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$var wire 1 F dec_o_ea_indirect $end
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$var wire 1 F dec_o_ea_ofs16 $end
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$var wire 4 G dec_o_dest_reg_addr [3:0] $end
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$var wire 1 G dec_o_ea_ofs0 $end
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$var wire 1 H dec_o_cond_taken $end
|
$var wire 1 H dec_o_ea_indirect $end
|
$var wire 1 I dec_o_alu_size $end
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$var wire 4 I dec_o_dest_reg_addr [3:0] $end
|
$var wire 5 J dec_o_alu_opcode [4:0] $end
|
$var wire 1 J dec_o_cond_taken $end
|
|
$var wire 1 K dec_o_alu_size $end
|
|
$var wire 5 L dec_o_alu_opcode [4:0] $end
|
$var wire 1 # cpu_we_o $end
|
$var wire 1 # cpu_we_o $end
|
$var wire 1 $ cpu_oe_o $end
|
$var wire 1 $ cpu_oe_o $end
|
$var wire 8 K cpu_data_o [7:0] $end
|
$var wire 8 M cpu_data_o [7:0] $end
|
$var wire 8 L cpu_data_i [7:0] $end
|
$var wire 8 N cpu_data_i [7:0] $end
|
$var wire 16 M cpu_addr_o [15:0] $end
|
$var wire 16 O cpu_addr_o [15:0] $end
|
$var wire 16 N alu_o_result [15:0] $end
|
$var wire 16 P alu_o_result [15:0] $end
|
$var wire 8 O alu_o_CCR [7:0] $end
|
$var wire 8 Q alu_o_CCR [7:0] $end
|
$var reg 4 P datamux_o_alu_in_left_path_addr [3:0] $end
|
$var reg 4 R datamux_o_alu_in_left_path_addr [3:0] $end
|
$var reg 16 Q datamux_o_alu_in_left_path_data [15:0] $end
|
$var reg 16 S datamux_o_alu_in_left_path_data [15:0] $end
|
$var reg 16 R datamux_o_alu_in_right_path_data [15:0] $end
|
$var reg 16 T datamux_o_alu_in_right_path_data [15:0] $end
|
$var reg 16 S datamux_o_dest [15:0] $end
|
$var reg 16 U datamux_o_dest [15:0] $end
|
$var reg 4 T datamux_o_dest_reg_addr [3:0] $end
|
$var reg 4 V datamux_o_dest_reg_addr [3:0] $end
|
$var reg 1 U k_clear_e $end
|
$var reg 1 W k_clear_e $end
|
$var reg 16 V k_cpu_addr [15:0] $end
|
$var reg 16 X k_cpu_addr [15:0] $end
|
$var reg 8 W k_cpu_data_o [7:0] $end
|
$var reg 8 Y k_cpu_data_o [7:0] $end
|
$var reg 1 $ k_cpu_oe $end
|
$var reg 1 $ k_cpu_oe $end
|
$var reg 1 # k_cpu_we $end
|
$var reg 1 # k_cpu_we $end
|
$var reg 1 X k_dec_su $end
|
$var reg 1 Z k_dec_su $end
|
$var reg 8 Y k_eahi [7:0] $end
|
$var reg 8 [ k_eahi [7:0] $end
|
$var reg 8 Z k_ealo [7:0] $end
|
$var reg 8 \ k_ealo [7:0] $end
|
$var reg 1 [ k_forced_mem_size $end
|
$var reg 1 ] k_forced_mem_size $end
|
$var reg 1 \ k_inc_pc $end
|
$var reg 1 ^ k_inc_pc $end
|
$var reg 1 ] k_inc_su $end
|
$var reg 1 _ k_inc_su $end
|
$var reg 8 ^ k_ind_ea [7:0] $end
|
$var reg 8 ` k_ind_ea [7:0] $end
|
$var reg 2 _ k_mem_dest [1:0] $end
|
$var reg 2 a k_mem_dest [1:0] $end
|
$var reg 8 ` k_memhi [7:0] $end
|
$var reg 8 b k_memhi [7:0] $end
|
$var reg 8 a k_memlo [7:0] $end
|
$var reg 8 c k_memlo [7:0] $end
|
$var reg 1 b k_mul_cnt $end
|
$var reg 1 d k_mul_cnt $end
|
$var reg 16 c k_new_pc [15:0] $end
|
$var reg 16 e k_new_pc [15:0] $end
|
$var reg 8 d k_ofshi [7:0] $end
|
$var reg 8 f k_ofshi [7:0] $end
|
$var reg 8 e k_ofslo [7:0] $end
|
$var reg 8 g k_ofslo [7:0] $end
|
$var reg 8 f k_opcode [7:0] $end
|
$var reg 8 h k_opcode [7:0] $end
|
$var reg 1 g k_p2_valid $end
|
$var reg 1 i k_p2_valid $end
|
$var reg 1 h k_p3_valid $end
|
$var reg 1 j k_p3_valid $end
|
$var reg 8 i k_postbyte [7:0] $end
|
$var reg 8 k k_postbyte [7:0] $end
|
$var reg 4 j k_pp_active_reg [3:0] $end
|
$var reg 4 l k_pp_active_reg [3:0] $end
|
$var reg 8 k k_pp_regs [7:0] $end
|
$var reg 8 m k_pp_regs [7:0] $end
|
$var reg 3 l k_reg_firq [2:0] $end
|
$var reg 3 n k_reg_firq [2:0] $end
|
$var reg 3 m k_reg_irq [2:0] $end
|
$var reg 3 o k_reg_irq [2:0] $end
|
$var reg 3 n k_reg_nmi [2:0] $end
|
$var reg 3 p k_reg_nmi [2:0] $end
|
$var reg 1 o k_set_e $end
|
$var reg 1 q k_set_e $end
|
$var reg 1 p k_write_dest $end
|
$var reg 1 r k_write_dest $end
|
$var reg 1 q k_write_exg $end
|
$var reg 1 s k_write_exg $end
|
$var reg 1 r k_write_pc $end
|
$var reg 1 t k_write_pc $end
|
$var reg 1 s k_write_post_incdec $end
|
$var reg 1 u k_write_post_incdec $end
|
$var reg 1 t k_write_tfr $end
|
$var reg 1 v k_write_tfr $end
|
$var reg 6 u next_mem_state [5:0] $end
|
$var reg 6 w next_mem_state [5:0] $end
|
$var reg 6 v next_push_state [5:0] $end
|
$var reg 6 x next_push_state [5:0] $end
|
$var reg 6 w next_state [5:0] $end
|
$var reg 6 y next_state [5:0] $end
|
$var reg 6 x state [5:0] $end
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$var reg 6 z state [5:0] $end
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$scope module alu $end
|
$scope module alu $end
|
$var wire 16 y a_in [15:0] $end
|
$var wire 16 { a_in [15:0] $end
|
$var wire 16 z b_in [15:0] $end
|
$var wire 16 | b_in [15:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 I sz_in $end
|
$var wire 1 K sz_in $end
|
$var wire 8 { q8_out [7:0] $end
|
$var wire 8 } q8_out [7:0] $end
|
$var wire 16 | q16_out [15:0] $end
|
$var wire 16 ~ q16_out [15:0] $end
|
$var wire 5 } opcode_in [4:0] $end
|
$var wire 5 !" opcode_in [4:0] $end
|
$var wire 8 ~ ccr8_out [7:0] $end
|
$var wire 8 "" ccr8_out [7:0] $end
|
$var wire 4 !" ccr16_out [3:0] $end
|
$var wire 4 #" ccr16_out [3:0] $end
|
$var wire 8 "" CCR [7:0] $end
|
$var wire 8 $" CCR [7:0] $end
|
$var reg 8 #" CCRo [7:0] $end
|
$var reg 8 %" CCRo [7:0] $end
|
$var reg 16 $" q_out [15:0] $end
|
$var reg 16 &" q_out [15:0] $end
|
$var reg 16 %" ra_in [15:0] $end
|
$var reg 16 '" ra_in [15:0] $end
|
$var reg 16 &" rb_in [15:0] $end
|
$var reg 16 (" rb_in [15:0] $end
|
$var reg 5 '" rop_in [4:0] $end
|
$var reg 5 )" rop_in [4:0] $end
|
$scope module alu16 $end
|
$scope module alu16 $end
|
$var wire 16 (" a_in [15:0] $end
|
$var wire 16 *" a_in [15:0] $end
|
$var wire 16 )" b_in [15:0] $end
|
$var wire 16 +" b_in [15:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 5 *" opcode_in [4:0] $end
|
$var wire 5 ," opcode_in [4:0] $end
|
$var wire 1 +" z_in $end
|
$var wire 1 -" z_in $end
|
$var wire 1 ," v_in $end
|
$var wire 1 ." v_in $end
|
$var wire 16 -" q16_mul [15:0] $end
|
$var wire 16 /" q16_mul [15:0] $end
|
$var wire 1 ." n_in $end
|
$var wire 1 0" n_in $end
|
$var wire 1 /" c_in $end
|
$var wire 1 1" c_in $end
|
$var wire 1 0" arith_v $end
|
$var wire 1 2" arith_v $end
|
$var wire 16 1" arith_q [15:0] $end
|
$var wire 16 3" arith_q [15:0] $end
|
$var wire 1 2" arith_c $end
|
$var wire 1 4" arith_c $end
|
$var wire 8 3" CCR [7:0] $end
|
$var wire 8 5" CCR [7:0] $end
|
$var reg 4 4" CCRo [3:0] $end
|
$var reg 4 6" CCRo [3:0] $end
|
$var reg 1 5" c16 $end
|
$var reg 1 7" c16 $end
|
$var reg 1 6" n16 $end
|
$var reg 1 8" n16 $end
|
$var reg 16 7" q16 [15:0] $end
|
$var reg 16 9" q16 [15:0] $end
|
$var reg 16 8" q_out [15:0] $end
|
$var reg 16 :" q_out [15:0] $end
|
$var reg 1 9" reg_n_in $end
|
$var reg 1 ;" reg_n_in $end
|
$var reg 1 :" reg_z_in $end
|
$var reg 1 <" reg_z_in $end
|
$var reg 16 ;" regq16 [15:0] $end
|
$var reg 16 =" regq16 [15:0] $end
|
$var reg 1 <" v16 $end
|
$var reg 1 >" v16 $end
|
$var reg 1 =" z16 $end
|
$var reg 1 ?" z16 $end
|
$scope module a16 $end
|
$scope module a16 $end
|
$var wire 16 >" a_in [15:0] $end
|
$var wire 16 @" a_in [15:0] $end
|
$var wire 16 ?" b_in [15:0] $end
|
$var wire 16 A" b_in [15:0] $end
|
$var wire 1 /" carry_in $end
|
$var wire 1 1" carry_in $end
|
$var wire 2 @" opcode_in [1:0] $end
|
$var wire 2 B" opcode_in [1:0] $end
|
$var reg 1 2" carry_out $end
|
$var reg 1 4" carry_out $end
|
$var reg 1 0" overflow_out $end
|
$var reg 1 2" overflow_out $end
|
$var reg 16 A" q_out [15:0] $end
|
$var reg 16 C" q_out [15:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module mulu $end
|
$scope module mulu $end
|
$var wire 8 B" a [7:0] $end
|
$var wire 8 D" a [7:0] $end
|
$var wire 8 C" b [7:0] $end
|
$var wire 8 E" b [7:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 16 D" q [15:0] $end
|
$var wire 16 F" q [15:0] $end
|
$var reg 16 E" pipe0 [15:0] $end
|
$var reg 16 G" pipe0 [15:0] $end
|
$var reg 16 F" pipe1 [15:0] $end
|
$var reg 16 H" pipe1 [15:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module alu8 $end
|
$scope module alu8 $end
|
$var wire 8 G" a_in [7:0] $end
|
$var wire 8 I" a_in [7:0] $end
|
$var wire 8 H" b_in [7:0] $end
|
$var wire 8 J" b_in [7:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 I" cneg8_r $end
|
$var wire 1 K" cneg8_r $end
|
$var wire 8 J" com8_r [7:0] $end
|
$var wire 8 L" com8_r [7:0] $end
|
$var wire 8 K" com8_w [7:0] $end
|
$var wire 8 M" com8_w [7:0] $end
|
$var wire 8 L" neg8_r [7:0] $end
|
$var wire 8 N" neg8_r [7:0] $end
|
$var wire 5 M" opcode_in [4:0] $end
|
$var wire 5 O" opcode_in [4:0] $end
|
$var wire 1 N" vcom8_r $end
|
$var wire 1 P" vcom8_r $end
|
$var wire 1 O" vneg8_r $end
|
$var wire 1 Q" vneg8_r $end
|
$var wire 1 P" z_in $end
|
$var wire 1 R" z_in $end
|
$var wire 1 Q" v_in $end
|
$var wire 1 S" v_in $end
|
$var wire 1 R" shift_v $end
|
$var wire 1 T" shift_v $end
|
$var wire 8 S" shift_q [7:0] $end
|
$var wire 8 U" shift_q [7:0] $end
|
$var wire 1 T" shift_c $end
|
$var wire 1 V" shift_c $end
|
$var wire 8 U" neg8_w [7:0] $end
|
$var wire 8 W" neg8_w [7:0] $end
|
$var wire 1 V" n_in $end
|
$var wire 1 X" n_in $end
|
$var wire 8 W" logic_q [7:0] $end
|
$var wire 8 Y" logic_q [7:0] $end
|
$var wire 1 X" h_in $end
|
$var wire 1 Z" h_in $end
|
$var wire 1 Y" daa_lnm9 $end
|
$var wire 1 [" daa_lnm9 $end
|
$var wire 4 Z" daa8l_r [3:0] $end
|
$var wire 4 \" daa8l_r [3:0] $end
|
$var wire 4 [" daa8h_r [3:0] $end
|
$var wire 4 ]" daa8h_r [3:0] $end
|
$var wire 1 \" cdaa8_r $end
|
$var wire 1 ^" cdaa8_r $end
|
$var wire 1 ]" ccom8_r $end
|
$var wire 1 _" ccom8_r $end
|
$var wire 1 ^" c_in $end
|
$var wire 1 `" c_in $end
|
$var wire 1 _" arith_v $end
|
$var wire 1 a" arith_v $end
|
$var wire 8 `" arith_q [7:0] $end
|
$var wire 8 b" arith_q [7:0] $end
|
$var wire 1 a" arith_h $end
|
$var wire 1 c" arith_h $end
|
$var wire 1 b" arith_c $end
|
$var wire 1 d" arith_c $end
|
$var wire 8 c" CCR [7:0] $end
|
$var wire 8 e" CCR [7:0] $end
|
$var reg 8 d" CCRo [7:0] $end
|
$var reg 8 f" CCRo [7:0] $end
|
$var reg 1 e" c8 $end
|
$var reg 1 g" c8 $end
|
$var reg 1 f" h8 $end
|
$var reg 1 h" h8 $end
|
$var reg 8 g" q8 [7:0] $end
|
$var reg 8 i" q8 [7:0] $end
|
$var reg 8 h" q_out [7:0] $end
|
$var reg 8 j" q_out [7:0] $end
|
$var reg 8 i" regq8 [7:0] $end
|
$var reg 8 k" regq8 [7:0] $end
|
$var reg 1 j" v8 $end
|
$var reg 1 l" v8 $end
|
$scope module a8 $end
|
$scope module a8 $end
|
$var wire 8 k" a_in [7:0] $end
|
$var wire 8 m" a_in [7:0] $end
|
$var wire 8 l" b_in [7:0] $end
|
$var wire 8 n" b_in [7:0] $end
|
$var wire 1 ^" carry_in $end
|
$var wire 1 `" carry_in $end
|
$var wire 1 X" half_c_in $end
|
$var wire 1 Z" half_c_in $end
|
$var wire 2 m" opcode_in [1:0] $end
|
$var wire 2 o" opcode_in [1:0] $end
|
$var reg 1 b" carry_out $end
|
$var wire 1 p" carry $end
|
$var reg 1 a" half_c_out $end
|
$var reg 1 d" carry_out $end
|
$var reg 1 _" overflow_out $end
|
$var reg 1 c" half_c_out $end
|
$var reg 8 n" q_out [7:0] $end
|
$var reg 1 a" overflow_out $end
|
|
$var reg 8 q" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module l8 $end
|
$scope module l8 $end
|
$var wire 8 o" a_in [7:0] $end
|
$var wire 8 r" a_in [7:0] $end
|
$var wire 8 p" b_in [7:0] $end
|
$var wire 8 s" b_in [7:0] $end
|
$var wire 2 q" opcode_in [1:0] $end
|
$var wire 2 t" opcode_in [1:0] $end
|
$var reg 8 r" q_out [7:0] $end
|
$var reg 8 u" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module s8 $end
|
$scope module s8 $end
|
$var wire 8 s" a_in [7:0] $end
|
$var wire 8 v" a_in [7:0] $end
|
$var wire 8 t" b_in [7:0] $end
|
$var wire 8 w" b_in [7:0] $end
|
$var wire 1 ^" carry_in $end
|
$var wire 1 `" carry_in $end
|
$var wire 3 u" opcode_in [2:0] $end
|
$var wire 3 x" opcode_in [2:0] $end
|
$var wire 1 Q" overflow_in $end
|
$var wire 1 S" overflow_in $end
|
$var wire 1 T" carry_out $end
|
$var wire 1 V" carry_out $end
|
$var reg 1 R" overflow_out $end
|
$var reg 1 T" overflow_out $end
|
$var reg 8 v" q_out [7:0] $end
|
$var reg 8 y" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_alu $end
|
$scope module dec_alu $end
|
$var wire 8 w" opcode [7:0] $end
|
$var wire 8 z" opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 i page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 j page3_valid $end
|
$var wire 8 x" postbyte0 [7:0] $end
|
$var wire 8 {" postbyte0 [7:0] $end
|
$var wire 1 9 dest_flags $end
|
$var wire 1 ; dest_flags $end
|
$var reg 5 y" alu_opcode [4:0] $end
|
$var reg 5 |" alu_opcode [4:0] $end
|
$var reg 2 z" dec_alu_right_path_mod [1:0] $end
|
$var reg 2 }" dec_alu_right_path_mod [1:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_ea $end
|
$scope module dec_ea $end
|
$var wire 8 {" eapostbyte [7:0] $end
|
$var wire 8 ~" eapostbyte [7:0] $end
|
$var wire 1 F isind $end
|
$var wire 1 H isind $end
|
$var reg 1 E noofs $end
|
$var reg 1 G noofs $end
|
$var reg 1 D ofs16 $end
|
$var reg 1 F ofs16 $end
|
$var reg 1 C ofs8 $end
|
$var reg 1 E ofs8 $end
|
$var reg 1 B write_post $end
|
$var reg 1 D write_post $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_op $end
|
$scope module dec_op $end
|
$var wire 8 |" opcode [7:0] $end
|
$var wire 8 !# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 i page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 j page3_valid $end
|
$var wire 8 }" postbyte0 [7:0] $end
|
$var wire 8 "# postbyte0 [7:0] $end
|
$var wire 4 ~" oplo [3:0] $end
|
$var wire 4 ## oplo [3:0] $end
|
$var reg 3 !# mode [2:0] $end
|
$var reg 3 $# mode [2:0] $end
|
$var reg 3 "# optype [2:0] $end
|
$var reg 3 %# optype [2:0] $end
|
$var reg 1 ## size $end
|
$var reg 1 &# size $end
|
$var reg 1 ; use_s $end
|
$var reg 1 = use_s $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_regs $end
|
$scope module dec_regs $end
|
$var wire 1 ( cpu_clk $end
|
$var wire 1 ( cpu_clk $end
|
$var wire 8 $# opcode [7:0] $end
|
$var wire 8 '# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 i page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 j page3_valid $end
|
$var wire 8 %# postbyte0 [7:0] $end
|
$var wire 8 (# postbyte0 [7:0] $end
|
$var wire 1 : write_dest $end
|
$var wire 1 < write_dest $end
|
$var wire 1 < source_size $end
|
$var wire 1 > source_size $end
|
$var wire 1 I result_size $end
|
$var wire 1 K result_size $end
|
$var reg 4 &# dest_reg [3:0] $end
|
$var reg 4 )# dest_reg [3:0] $end
|
$var reg 4 '# dest_reg_o [3:0] $end
|
$var reg 4 *# dest_reg_o [3:0] $end
|
$var reg 4 (# path_left_addr [3:0] $end
|
$var reg 4 +# path_left_addr [3:0] $end
|
$var reg 4 )# path_left_addr_o [3:0] $end
|
$var reg 4 ,# path_left_addr_o [3:0] $end
|
$var reg 4 *# path_right_addr [3:0] $end
|
$var reg 4 -# path_right_addr [3:0] $end
|
$var reg 4 +# path_right_addr_o [3:0] $end
|
$var reg 4 .# path_right_addr_o [3:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module regs $end
|
$scope module regs $end
|
$var wire 8 ,# CCR_in [7:0] $end
|
$var wire 8 /# CCR_in [7:0] $end
|
$var wire 1 U clear_e $end
|
$var wire 1 W clear_e $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 16 -# data_w [15:0] $end
|
$var wire 16 0# data_w [15:0] $end
|
$var wire 1 X dec_su $end
|
$var wire 1 Z dec_su $end
|
$var wire 16 .# eamem_addr_o [15:0] $end
|
$var wire 16 1# eamem_addr_o [15:0] $end
|
$var wire 8 /# eapostbyte [7:0] $end
|
$var wire 8 2# eapostbyte [7:0] $end
|
$var wire 4 0# exg_dest_r [3:0] $end
|
$var wire 4 3# exg_dest_r [3:0] $end
|
$var wire 1 \ inc_pc $end
|
$var wire 1 ^ inc_pc $end
|
$var wire 1 ] inc_su $end
|
$var wire 1 _ inc_su $end
|
$var wire 16 1# new_pc [15:0] $end
|
$var wire 16 4# new_pc [15:0] $end
|
$var wire 16 2# offset16 [15:0] $end
|
$var wire 16 5# offset16 [15:0] $end
|
$var wire 4 3# path_left_addr [3:0] $end
|
$var wire 4 6# path_left_addr [3:0] $end
|
$var wire 4 4# path_right_addr [3:0] $end
|
$var wire 4 7# path_right_addr [3:0] $end
|
$var wire 8 5# reg_dp [7:0] $end
|
$var wire 8 8# reg_dp [7:0] $end
|
$var wire 16 6# reg_pc [15:0] $end
|
$var wire 16 9# reg_pc [15:0] $end
|
$var wire 1 o set_e $end
|
$var wire 1 q set_e $end
|
$var wire 1 ; use_s $end
|
$var wire 1 = use_s $end
|
$var wire 1 q write_exg $end
|
$var wire 1 s write_exg $end
|
$var wire 1 7# write_flags $end
|
$var wire 1 :# write_flags $end
|
$var wire 1 r write_pc $end
|
$var wire 1 t write_pc $end
|
$var wire 1 s write_post $end
|
$var wire 1 u write_post $end
|
$var wire 1 p write_reg $end
|
$var wire 1 r write_reg $end
|
$var wire 4 8# write_reg_addr [3:0] $end
|
$var wire 4 ;# write_reg_addr [3:0] $end
|
$var wire 1 t write_tfr $end
|
$var wire 1 v write_tfr $end
|
$var wire 4 9# right_reg [3:0] $end
|
$var wire 4 <# right_reg [3:0] $end
|
$var wire 16 :# right [15:0] $end
|
$var wire 16 =# right [15:0] $end
|
$var wire 16 ;# reg_su [15:0] $end
|
$var wire 16 ># reg_su [15:0] $end
|
$var wire 16 <# pc_plus_1 [15:0] $end
|
$var wire 16 ?# pc_plus_1 [15:0] $end
|
$var wire 16 =# left [15:0] $end
|
$var wire 16 @# left [15:0] $end
|
$var wire 16 ># eamem_addr [15:0] $end
|
$var wire 16 A# eamem_addr [15:0] $end
|
$var wire 16 ?# ea_reg_post [15:0] $end
|
$var wire 16 B# ea_reg_post [15:0] $end
|
$var wire 8 @# CCR_o [7:0] $end
|
$var wire 8 C# CCR_o [7:0] $end
|
$var reg 8 A# ACCA [7:0] $end
|
$var reg 8 D# ACCA [7:0] $end
|
$var reg 8 B# ACCB [7:0] $end
|
$var reg 8 E# ACCB [7:0] $end
|
$var reg 8 C# DP [7:0] $end
|
$var reg 8 F# DP [7:0] $end
|
$var reg 16 D# IX [15:0] $end
|
$var reg 16 G# IX [15:0] $end
|
$var reg 16 E# IY [15:0] $end
|
$var reg 16 H# IY [15:0] $end
|
$var reg 16 F# PC [15:0] $end
|
$var reg 16 I# PC [15:0] $end
|
$var reg 16 G# SS [15:0] $end
|
$var reg 16 J# SS [15:0] $end
|
$var reg 16 H# SU [15:0] $end
|
$var reg 16 K# SU [15:0] $end
|
$var reg 1 I# cff $end
|
$var reg 1 L# cff $end
|
$var reg 1 J# eflag $end
|
$var reg 1 M# eflag $end
|
$var reg 1 K# fflag $end
|
$var reg 1 N# fflag $end
|
$var reg 1 L# hflag $end
|
$var reg 1 O# hflag $end
|
$var reg 1 M# intff $end
|
$var reg 1 P# intff $end
|
$var reg 1 N# nff $end
|
$var reg 1 Q# nff $end
|
$var reg 16 O# path_left_data [15:0] $end
|
$var reg 16 R# path_left_data [15:0] $end
|
$var reg 16 P# path_right_data [15:0] $end
|
$var reg 16 S# path_right_data [15:0] $end
|
$var reg 1 Q# vff $end
|
$var reg 1 T# vff $end
|
$var reg 1 R# zff $end
|
$var reg 1 U# zff $end
|
$scope module ea $end
|
$scope module ea $end
|
$var wire 8 S# acca [7:0] $end
|
$var wire 8 V# acca [7:0] $end
|
$var wire 8 T# accb [7:0] $end
|
$var wire 8 W# accb [7:0] $end
|
$var wire 16 U# ea_reg_post_o [15:0] $end
|
$var wire 16 X# ea_reg_post_o [15:0] $end
|
$var wire 16 V# eamem_addr_o [15:0] $end
|
$var wire 16 Y# eamem_addr_o [15:0] $end
|
$var wire 8 W# eapostbyte [7:0] $end
|
$var wire 8 Z# eapostbyte [7:0] $end
|
$var wire 16 X# ix [15:0] $end
|
$var wire 16 [# ix [15:0] $end
|
$var wire 16 Y# iy [15:0] $end
|
$var wire 16 \# iy [15:0] $end
|
$var wire 16 Z# offset16 [15:0] $end
|
$var wire 16 ]# offset16 [15:0] $end
|
$var wire 16 [# pc [15:0] $end
|
$var wire 16 ^# pc [15:0] $end
|
$var wire 16 \# s [15:0] $end
|
$var wire 16 _# s [15:0] $end
|
$var wire 16 ]# u [15:0] $end
|
$var wire 16 `# u [15:0] $end
|
$var reg 16 ^# ea_reg [15:0] $end
|
$var reg 16 a# ea_reg [15:0] $end
|
$var reg 16 _# ea_reg_post [15:0] $end
|
$var reg 16 b# ea_reg_post [15:0] $end
|
$var reg 16 `# eamem_addr [15:0] $end
|
$var reg 16 c# eamem_addr [15:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module test_cond $end
|
$scope module test_cond $end
|
$var wire 8 a# CCR [7:0] $end
|
$var wire 8 d# CCR [7:0] $end
|
$var wire 8 b# opcode [7:0] $end
|
$var wire 8 e# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 i page2_valid $end
|
$var wire 8 c# postbyte0 [7:0] $end
|
$var wire 8 f# postbyte0 [7:0] $end
|
$var wire 8 d# op [7:0] $end
|
$var wire 8 g# op [7:0] $end
|
$var reg 1 H cond_taken $end
|
$var reg 1 J cond_taken $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module imem $end
|
$scope module imem $end
|
$var wire 16 e# addr [15:0] $end
|
$var wire 16 h# addr [15:0] $end
|
$var wire 8 f# data_i [7:0] $end
|
$var wire 8 i# data_i [7:0] $end
|
$var wire 8 g# data_o [7:0] $end
|
$var wire 8 j# data_o [7:0] $end
|
$var wire 8 h# mem0 [7:0] $end
|
$var wire 8 k# mem0 [7:0] $end
|
$var wire 8 i# mem1 [7:0] $end
|
$var wire 8 l# mem1 [7:0] $end
|
$var wire 8 j# mem2 [7:0] $end
|
$var wire 8 m# mem2 [7:0] $end
|
$var wire 8 k# mem3 [7:0] $end
|
$var wire 8 n# mem3 [7:0] $end
|
$var wire 1 l# oe $end
|
$var wire 1 o# oe $end
|
$var wire 1 m# we $end
|
$var wire 1 p# we $end
|
$var reg 8 n# latecheddata [7:0] $end
|
$var reg 8 q# latecheddata [7:0] $end
|
|
$var integer 32 r# i [31:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$enddefinitions $end
|
$enddefinitions $end
|
#0
|
#0
|
$dumpvars
|
$dumpvars
|
bx n#
|
b10000000000000000 r#
|
1m#
|
bx q#
|
1l#
|
1p#
|
b111101 k#
|
1o#
|
b10111011 j#
|
b10100101 n#
|
b10101010 i#
|
b10100101 m#
|
b11001100 h#
|
b10100101 l#
|
|
b10100101 k#
|
|
bx j#
|
|
bx i#
|
|
bx h#
|
bx g#
|
bx g#
|
bx f#
|
bx f#
|
bx e#
|
bx e#
|
bx d#
|
b0 d#
|
bx c#
|
bx c#
|
bx b#
|
bx b#
|
b0 a#
|
bx a#
|
bx `#
|
b111000000000 `#
|
bx _#
|
b111100000000 _#
|
bx ^#
|
b1111111111111110 ^#
|
b111000000000 ]#
|
bx ]#
|
b111100000000 \#
|
b1010010101011010 \#
|
b1111111111111110 [#
|
b0 [#
|
bx Z#
|
bx Z#
|
b1010010101011010 Y#
|
bx Y#
|
b0 X#
|
bx X#
|
bx W#
|
bx W#
|
bx V#
|
bx V#
|
bx U#
|
0U#
|
bx T#
|
0T#
|
bx S#
|
b1111111111111111 S#
|
0R#
|
b1111111111111111 R#
|
0Q#
|
0Q#
|
b1111111111111111 P#
|
0P#
|
b1111111111111111 O#
|
0O#
|
0N#
|
0N#
|
0M#
|
0M#
|
0L#
|
0L#
|
0K#
|
b111000000000 K#
|
0J#
|
b111100000000 J#
|
0I#
|
b1111111111111110 I#
|
b111000000000 H#
|
b1010010101011010 H#
|
b111100000000 G#
|
b0 G#
|
b1111111111111110 F#
|
b0 F#
|
b1010010101011010 E#
|
bx E#
|
b0 D#
|
bx D#
|
b0 C#
|
b0 C#
|
bx B#
|
bx B#
|
bx A#
|
bx A#
|
b0 @#
|
b0 @#
|
bx ?#
|
b1111111111111111 ?#
|
bx >#
|
b111x00000000 >#
|
b0 =#
|
b1111111111111111 =#
|
b1111111111111111 <#
|
bx <#
|
b111x00000000 ;#
|
bx ;#
|
b1111111111111111 :#
|
0:#
|
bx 9#
|
b1111111111111110 9#
|
bx 8#
|
b0 8#
|
07#
|
bx 7#
|
b1111111111111110 6#
|
bx 6#
|
b0 5#
|
bx 5#
|
bx 4#
|
bx 4#
|
bx 3#
|
bx 3#
|
bx 2#
|
bx 2#
|
bx 1#
|
bx 1#
|
bx 0#
|
b0 0#
|
bx /#
|
b100 /#
|
bx .#
|
bx .#
|
b0 -#
|
bx -#
|
b100 ,#
|
bx ,#
|
bx +#
|
bx +#
|
bx *#
|
bx *#
|
bx )#
|
bx )#
|
bx (#
|
bx (#
|
bx '#
|
bx '#
|
bx &#
|
x&#
|
bx %#
|
bx %#
|
bx $#
|
bx $#
|
x##
|
bx ##
|
bx "#
|
bx "#
|
bx !#
|
bx !#
|
bx ~"
|
bx ~"
|
bx }"
|
bx }"
|
bx |"
|
bx |"
|
| Line 456... |
Line 464... |
bx u"
|
bx u"
|
bx t"
|
bx t"
|
bx s"
|
bx s"
|
bx r"
|
bx r"
|
bx q"
|
bx q"
|
bx p"
|
0p"
|
bx o"
|
bx o"
|
bx n"
|
bx n"
|
bx m"
|
bx m"
|
bx l"
|
0l"
|
bx k"
|
bx k"
|
0j"
|
b0 j"
|
bx i"
|
b0 i"
|
b0 h"
|
0h"
|
b0 g"
|
0g"
|
0f"
|
b100 f"
|
0e"
|
b0 e"
|
b100 d"
|
xd"
|
b0 c"
|
xc"
|
xb"
|
bx b"
|
xa"
|
xa"
|
bx `"
|
0`"
|
x_"
|
x_"
|
0^"
|
x^"
|
x]"
|
bx ]"
|
x\"
|
bx \"
|
bx ["
|
x["
|
bx Z"
|
0Z"
|
xY"
|
bx Y"
|
0X"
|
0X"
|
bx W"
|
bx W"
|
0V"
|
xV"
|
bx U"
|
bx U"
|
xT"
|
0T"
|
bx S"
|
0S"
|
0R"
|
0R"
|
0Q"
|
xQ"
|
0P"
|
0P"
|
xO"
|
bx O"
|
0N"
|
bx N"
|
bx M"
|
bx M"
|
bx L"
|
bx L"
|
bx K"
|
xK"
|
bx J"
|
bx J"
|
xI"
|
bx I"
|
bx H"
|
bx H"
|
bx G"
|
bx G"
|
bx F"
|
bx F"
|
bx E"
|
bx E"
|
bx D"
|
bx D"
|
bx C"
|
bx C"
|
bx B"
|
bx B"
|
bx A"
|
bx A"
|
bx @"
|
bx @"
|
bx ?"
|
1?"
|
bx >"
|
0>"
|
1="
|
bx ="
|
0<"
|
x<"
|
bx ;"
|
x;"
|
x:"
|
b0 :"
|
x9"
|
b0 9"
|
b0 8"
|
08"
|
b0 7"
|
07"
|
06"
|
b100 6"
|
05"
|
b0 5"
|
b100 4"
|
x4"
|
b0 3"
|
bx 3"
|
x2"
|
x2"
|
bx 1"
|
01"
|
x0"
|
00"
|
0/"
|
bx /"
|
0."
|
0."
|
bx -"
|
0-"
|
0,"
|
bx ,"
|
0+"
|
bx +"
|
bx *"
|
bx *"
|
bx )"
|
bx )"
|
bx ("
|
bx ("
|
bx '"
|
bx '"
|
bx &"
|
b0 &"
|
bx %"
|
b100 %"
|
b0 $"
|
b0 $"
|
b100 #"
|
b100 #"
|
b0 ""
|
b100 ""
|
b100 !"
|
bx !"
|
b100 ~
|
b0 ~
|
bx }
|
b0 }
|
b0 |
|
bx |
|
b0 {
|
b1111111111111111 {
|
bx z
|
b0 z
|
b1111111111111111 y
|
bx y
|
b0 x
|
bx x
|
bx w
|
bx w
|
bx v
|
0v
|
bx u
|
xu
|
0t
|
xt
|
xs
|
0s
|
xr
|
0r
|
0q
|
xq
|
xp
|
b0 p
|
xo
|
b0 o
|
b0 n
|
b0 n
|
b0 m
|
bx m
|
b0 l
|
bx l
|
bx k
|
bx k
|
bx j
|
xj
|
bx i
|
xi
|
xh
|
bx h
|
xg
|
bx g
|
bx f
|
bx f
|
bx e
|
bx e
|
bx d
|
0d
|
bx c
|
bx c
|
0b
|
bx b
|
bx a
|
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#7046
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