| Line 1... |
Line 1... |
$date
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$date
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Sun Jun 22 08:16:49 2014
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Wed Jul 02 12:37:24 2014
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$end
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$end
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$version
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$version
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Icarus Verilog
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Icarus Verilog
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$end
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$end
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$timescale
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$timescale
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1ns
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1ns
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$end
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$end
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$scope module tb $end
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$scope module tb $end
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$var wire 16 ! addr_o [15:0] $end
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$var wire 16 ! addr [15:0] $end
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$var wire 8 " data_o_o [7:0] $end
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$var wire 16 " addr_o [15:0] $end
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$var wire 1 # we $end
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$var wire 8 # data_i [7:0] $end
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$var wire 1 $ oe $end
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$var wire 8 $ data_o [7:0] $end
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$var wire 8 % data_o [7:0] $end
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$var wire 8 % data_o_o [7:0] $end
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$var wire 8 & data_i [7:0] $end
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$var wire 1 & oe $end
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$var wire 16 ' addr [15:0] $end
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$var wire 1 ' we $end
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$var reg 1 ( clk $end
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$var reg 1 ( clk $end
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$var reg 1 ) reset $end
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$var reg 1 ) reset $end
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$scope module cpu $end
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$scope module cpu $end
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$var wire 1 ( cpu_clk $end
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$var wire 8 * alu_o_CCR [7:0] $end
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$var wire 1 * cpu_firq_n $end
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$var wire 16 + alu_o_result [15:0] $end
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$var wire 1 + cpu_irq_n $end
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$var wire 16 , cpu_addr_o [15:0] $end
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$var wire 1 , cpu_nmi_n $end
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$var wire 1 - cpu_clk $end
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$var wire 1 ) cpu_reset $end
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$var wire 8 . cpu_data_i [7:0] $end
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$var wire 6 - cpu_state_o [5:0] $end
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$var wire 8 / cpu_data_o [7:0] $end
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$var wire 1 . debug_clk $end
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$var wire 1 0 cpu_firq_n $end
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$var wire 1 / debug_data_o $end
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$var wire 1 1 cpu_irq_n $end
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$var wire 1 0 k_firq_req $end
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$var wire 1 2 cpu_nmi_n $end
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$var wire 1 1 k_irq_req $end
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$var wire 1 & cpu_oe_o $end
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$var wire 1 2 k_nmi_req $end
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$var wire 1 3 cpu_reset $end
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$var wire 1 3 k_reset $end
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$var wire 6 4 cpu_state_o [5:0] $end
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$var wire 16 4 regs_o_su [15:0] $end
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$var wire 1 ' cpu_we_o $end
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$var wire 16 5 regs_o_right_path_data [15:0] $end
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$var wire 1 5 debug_clk $end
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$var wire 16 6 regs_o_pc [15:0] $end
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$var wire 1 6 debug_data_o $end
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$var wire 16 7 regs_o_left_path_data [15:0] $end
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$var wire 4 7 dec_lo_dest_reg_addr [3:0] $end
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$var wire 16 8 regs_o_eamem_addr [15:0] $end
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$var wire 4 8 dec_lo_left_path_addr [3:0] $end
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$var wire 8 9 regs_o_dp [7:0] $end
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$var wire 4 9 dec_lo_right_path_addr [3:0] $end
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$var wire 8 : regs_o_CCR [7:0] $end
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$var wire 5 : dec_o_alu_opcode [4:0] $end
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$var wire 1 ; dec_o_write_flags $end
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$var wire 1 ; dec_o_alu_size $end
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$var wire 1 < dec_o_wdest $end
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$var wire 1 < dec_o_cond_taken $end
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$var wire 1 = dec_o_use_s $end
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$var wire 4 = dec_o_dest_reg_addr [3:0] $end
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$var wire 1 > dec_o_source_size $end
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$var wire 1 > dec_o_ea_indirect $end
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$var wire 2 ? dec_o_right_path_mod [1:0] $end
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$var wire 1 ? dec_o_ea_ofs0 $end
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$var wire 4 @ dec_o_right_path_addr [3:0] $end
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$var wire 1 @ dec_o_ea_ofs16 $end
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$var wire 3 A dec_o_p1_optype [2:0] $end
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$var wire 1 A dec_o_ea_ofs8 $end
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$var wire 3 B dec_o_p1_mode [2:0] $end
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$var wire 1 B dec_o_ea_wpost $end
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$var wire 4 C dec_o_left_path_addr [3:0] $end
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$var wire 4 C dec_o_left_path_addr [3:0] $end
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$var wire 1 D dec_o_ea_wpost $end
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$var wire 3 D dec_o_p1_mode [2:0] $end
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$var wire 1 E dec_o_ea_ofs8 $end
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$var wire 3 E dec_o_p1_optype [2:0] $end
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$var wire 1 F dec_o_ea_ofs16 $end
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$var wire 4 F dec_o_right_path_addr [3:0] $end
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$var wire 1 G dec_o_ea_ofs0 $end
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$var wire 2 G dec_o_right_path_mod [1:0] $end
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$var wire 1 H dec_o_ea_indirect $end
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$var wire 1 H dec_o_source_size $end
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$var wire 4 I dec_o_dest_reg_addr [3:0] $end
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$var wire 1 I dec_o_use_s $end
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$var wire 1 J dec_o_cond_taken $end
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$var wire 1 J dec_o_wdest $end
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$var wire 1 K dec_o_alu_size $end
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$var wire 1 K dec_o_write_flags $end
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$var wire 5 L dec_o_alu_opcode [4:0] $end
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$var wire 1 L k_firq_req $end
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$var wire 1 # cpu_we_o $end
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$var wire 1 M k_irq_req $end
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$var wire 1 $ cpu_oe_o $end
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$var wire 1 N k_nmi_req $end
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$var wire 8 M cpu_data_o [7:0] $end
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$var wire 1 O k_reset $end
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$var wire 8 N cpu_data_i [7:0] $end
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$var wire 8 P regs_o_CCR [7:0] $end
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$var wire 16 O cpu_addr_o [15:0] $end
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$var wire 8 Q regs_o_dp [7:0] $end
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$var wire 16 P alu_o_result [15:0] $end
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$var wire 16 R regs_o_eamem_addr [15:0] $end
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$var wire 8 Q alu_o_CCR [7:0] $end
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$var wire 16 S regs_o_left_path_data [15:0] $end
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$var reg 4 R datamux_o_alu_in_left_path_addr [3:0] $end
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$var wire 16 T regs_o_pc [15:0] $end
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$var reg 16 S datamux_o_alu_in_left_path_data [15:0] $end
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$var wire 16 U regs_o_right_path_data [15:0] $end
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$var reg 16 T datamux_o_alu_in_right_path_data [15:0] $end
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$var wire 16 V regs_o_su [15:0] $end
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$var reg 16 U datamux_o_dest [15:0] $end
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$var reg 4 W datamux_o_alu_in_left_path_addr [3:0] $end
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$var reg 4 V datamux_o_dest_reg_addr [3:0] $end
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$var reg 16 X datamux_o_alu_in_left_path_data [15:0] $end
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$var reg 1 W k_clear_e $end
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$var reg 16 Y datamux_o_alu_in_right_path_data [15:0] $end
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$var reg 16 X k_cpu_addr [15:0] $end
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$var reg 16 Z datamux_o_dest [15:0] $end
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$var reg 8 Y k_cpu_data_o [7:0] $end
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$var reg 4 [ datamux_o_dest_reg_addr [3:0] $end
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$var reg 1 $ k_cpu_oe $end
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$var reg 1 \ k_clear_e $end
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$var reg 1 # k_cpu_we $end
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$var reg 16 ] k_cpu_addr [15:0] $end
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$var reg 1 Z k_dec_su $end
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$var reg 8 ^ k_cpu_data_o [7:0] $end
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$var reg 8 [ k_eahi [7:0] $end
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$var reg 1 _ k_cpu_oe $end
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$var reg 8 \ k_ealo [7:0] $end
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$var reg 1 ` k_cpu_we $end
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$var reg 1 ] k_forced_mem_size $end
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$var reg 1 a k_dec_su $end
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$var reg 1 ^ k_inc_pc $end
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$var reg 8 b k_eahi [7:0] $end
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$var reg 1 _ k_inc_su $end
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$var reg 8 c k_ealo [7:0] $end
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$var reg 8 ` k_ind_ea [7:0] $end
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$var reg 1 d k_forced_mem_size $end
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$var reg 2 a k_mem_dest [1:0] $end
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$var reg 1 e k_inc_pc $end
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$var reg 8 b k_memhi [7:0] $end
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$var reg 1 f k_inc_su $end
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$var reg 8 c k_memlo [7:0] $end
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$var reg 8 g k_ind_ea [7:0] $end
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$var reg 1 d k_mul_cnt $end
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$var reg 2 h k_mem_dest [1:0] $end
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$var reg 16 e k_new_pc [15:0] $end
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$var reg 8 i k_memhi [7:0] $end
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$var reg 8 f k_ofshi [7:0] $end
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$var reg 8 j k_memlo [7:0] $end
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$var reg 8 g k_ofslo [7:0] $end
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$var reg 1 k k_mul_cnt $end
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$var reg 8 h k_opcode [7:0] $end
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$var reg 16 l k_new_pc [15:0] $end
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$var reg 1 i k_p2_valid $end
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$var reg 8 m k_ofshi [7:0] $end
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$var reg 1 j k_p3_valid $end
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$var reg 8 n k_ofslo [7:0] $end
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$var reg 8 k k_postbyte [7:0] $end
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$var reg 8 o k_opcode [7:0] $end
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$var reg 4 l k_pp_active_reg [3:0] $end
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$var reg 1 p k_p2_valid $end
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$var reg 8 m k_pp_regs [7:0] $end
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$var reg 1 q k_p3_valid $end
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$var reg 3 n k_reg_firq [2:0] $end
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$var reg 8 r k_postbyte [7:0] $end
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$var reg 3 o k_reg_irq [2:0] $end
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$var reg 4 s k_pp_active_reg [3:0] $end
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$var reg 3 p k_reg_nmi [2:0] $end
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$var reg 8 t k_pp_regs [7:0] $end
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$var reg 1 q k_set_e $end
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$var reg 3 u k_reg_firq [2:0] $end
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$var reg 1 r k_write_dest $end
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$var reg 3 v k_reg_irq [2:0] $end
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$var reg 1 s k_write_exg $end
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$var reg 3 w k_reg_nmi [2:0] $end
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$var reg 1 t k_write_pc $end
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$var reg 1 x k_set_e $end
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$var reg 1 u k_write_post_incdec $end
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$var reg 1 y k_write_dest $end
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$var reg 1 v k_write_tfr $end
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$var reg 1 z k_write_exg $end
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$var reg 6 w next_mem_state [5:0] $end
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$var reg 1 { k_write_pc $end
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$var reg 6 x next_push_state [5:0] $end
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$var reg 1 | k_write_post_incdec $end
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$var reg 6 y next_state [5:0] $end
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$var reg 1 } k_write_tfr $end
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$var reg 6 z state [5:0] $end
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$var reg 6 ~ next_mem_state [5:0] $end
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$var reg 6 !" next_push_state [5:0] $end
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$var reg 6 "" next_state [5:0] $end
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$var reg 6 #" state [5:0] $end
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$scope module alu $end
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$scope module alu $end
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$var wire 16 { a_in [15:0] $end
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$var wire 16 | b_in [15:0] $end
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$var wire 1 ( clk_in $end
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$var wire 1 K sz_in $end
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$var wire 8 } q8_out [7:0] $end
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$var wire 16 ~ q16_out [15:0] $end
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$var wire 5 !" opcode_in [4:0] $end
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$var wire 8 "" ccr8_out [7:0] $end
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$var wire 4 #" ccr16_out [3:0] $end
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$var wire 8 $" CCR [7:0] $end
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$var wire 8 $" CCR [7:0] $end
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$var reg 8 %" CCRo [7:0] $end
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$var wire 16 %" a_in [15:0] $end
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$var reg 16 &" q_out [15:0] $end
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$var wire 16 &" b_in [15:0] $end
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$var reg 16 '" ra_in [15:0] $end
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$var wire 4 '" ccr16_out [3:0] $end
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$var reg 16 (" rb_in [15:0] $end
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$var wire 8 (" ccr8_out [7:0] $end
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$var reg 5 )" rop_in [4:0] $end
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$var wire 1 - clk_in $end
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$scope module alu16 $end
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$var wire 5 )" opcode_in [4:0] $end
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$var wire 16 *" a_in [15:0] $end
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$var wire 16 *" q16_out [15:0] $end
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$var wire 16 +" b_in [15:0] $end
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$var wire 8 +" q8_out [7:0] $end
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$var wire 1 ( clk_in $end
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$var wire 1 ; sz_in $end
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$var wire 5 ," opcode_in [4:0] $end
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$var reg 8 ," CCRo [7:0] $end
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$var wire 1 -" z_in $end
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$var reg 16 -" q_out [15:0] $end
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$var wire 1 ." v_in $end
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$var reg 16 ." ra_in [15:0] $end
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$var wire 16 /" q16_mul [15:0] $end
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$var reg 16 /" rb_in [15:0] $end
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$var wire 1 0" n_in $end
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$var reg 5 0" rop_in [4:0] $end
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$var wire 1 1" c_in $end
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$var wire 1 2" arith_v $end
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$var wire 16 3" arith_q [15:0] $end
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$var wire 1 4" arith_c $end
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$var wire 8 5" CCR [7:0] $end
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$var reg 4 6" CCRo [3:0] $end
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$var reg 1 7" c16 $end
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$var reg 1 8" n16 $end
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$var reg 16 9" q16 [15:0] $end
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$var reg 16 :" q_out [15:0] $end
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$var reg 1 ;" reg_n_in $end
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$var reg 1 <" reg_z_in $end
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$var reg 16 =" regq16 [15:0] $end
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$var reg 1 >" v16 $end
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$var reg 1 ?" z16 $end
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$scope module a16 $end
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$var wire 16 @" a_in [15:0] $end
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$var wire 16 A" b_in [15:0] $end
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$var wire 1 1" carry_in $end
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$var wire 2 B" opcode_in [1:0] $end
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$var reg 1 4" carry_out $end
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$var reg 1 2" overflow_out $end
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$var reg 16 C" q_out [15:0] $end
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$upscope $end
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$scope module mulu $end
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$var wire 8 D" a [7:0] $end
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$var wire 8 E" b [7:0] $end
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$var wire 1 ( clk_in $end
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$var wire 16 F" q [15:0] $end
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$var reg 16 G" pipe0 [15:0] $end
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$var reg 16 H" pipe1 [15:0] $end
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$upscope $end
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$upscope $end
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$scope module alu8 $end
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$scope module alu8 $end
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$var wire 8 I" a_in [7:0] $end
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$var wire 8 1" CCR [7:0] $end
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$var wire 8 J" b_in [7:0] $end
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$var wire 8 2" a_in [7:0] $end
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$var wire 1 ( clk_in $end
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$var wire 1 3" arith_c $end
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$var wire 1 K" cneg8_r $end
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$var wire 1 4" arith_h $end
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$var wire 8 L" com8_r [7:0] $end
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$var wire 8 5" arith_q [7:0] $end
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$var wire 8 M" com8_w [7:0] $end
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$var wire 1 6" arith_v $end
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$var wire 8 N" neg8_r [7:0] $end
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$var wire 8 7" b_in [7:0] $end
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$var wire 5 O" opcode_in [4:0] $end
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$var wire 1 8" c_in $end
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$var wire 1 P" vcom8_r $end
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$var wire 1 9" ccom8_r $end
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$var wire 1 Q" vneg8_r $end
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$var wire 1 :" cdaa8_r $end
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$var wire 1 R" z_in $end
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$var wire 1 - clk_in $end
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$var wire 1 S" v_in $end
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$var wire 1 ;" cneg8_r $end
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$var wire 1 T" shift_v $end
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$var wire 8 <" com8_r [7:0] $end
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$var wire 8 U" shift_q [7:0] $end
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$var wire 8 =" com8_w [7:0] $end
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$var wire 1 V" shift_c $end
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$var wire 4 >" daa8h_r [3:0] $end
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$var wire 8 W" neg8_w [7:0] $end
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$var wire 4 ?" daa8l_r [3:0] $end
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$var wire 1 X" n_in $end
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$var wire 1 @" daa_lnm9 $end
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$var wire 8 Y" logic_q [7:0] $end
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$var wire 1 A" h_in $end
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$var wire 1 Z" h_in $end
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$var wire 8 B" logic_q [7:0] $end
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$var wire 1 [" daa_lnm9 $end
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$var wire 1 C" n_in $end
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$var wire 4 \" daa8l_r [3:0] $end
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$var wire 8 D" neg8_r [7:0] $end
|
$var wire 4 ]" daa8h_r [3:0] $end
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$var wire 8 E" neg8_w [7:0] $end
|
$var wire 1 ^" cdaa8_r $end
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$var wire 5 F" opcode_in [4:0] $end
|
$var wire 1 _" ccom8_r $end
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$var wire 1 G" shift_c $end
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$var wire 1 `" c_in $end
|
$var wire 8 H" shift_q [7:0] $end
|
$var wire 1 a" arith_v $end
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$var wire 1 I" shift_v $end
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$var wire 8 b" arith_q [7:0] $end
|
$var wire 1 J" v_in $end
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$var wire 1 c" arith_h $end
|
$var wire 1 K" vcom8_r $end
|
$var wire 1 d" arith_c $end
|
$var wire 1 L" vneg8_r $end
|
$var wire 8 e" CCR [7:0] $end
|
$var wire 1 M" z_in $end
|
$var reg 8 f" CCRo [7:0] $end
|
$var reg 8 N" CCRo [7:0] $end
|
$var reg 1 g" c8 $end
|
$var reg 1 O" c8 $end
|
$var reg 1 h" h8 $end
|
$var reg 1 P" h8 $end
|
$var reg 8 i" q8 [7:0] $end
|
$var reg 8 Q" q8 [7:0] $end
|
$var reg 8 j" q_out [7:0] $end
|
$var reg 8 R" q_out [7:0] $end
|
$var reg 8 k" regq8 [7:0] $end
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$var reg 8 S" regq8 [7:0] $end
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$var reg 1 l" v8 $end
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$var reg 1 T" v8 $end
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$scope module a8 $end
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$var wire 8 m" a_in [7:0] $end
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$var wire 8 n" b_in [7:0] $end
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$var wire 1 `" carry_in $end
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$var wire 1 Z" half_c_in $end
|
|
$var wire 2 o" opcode_in [1:0] $end
|
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$var wire 1 p" carry $end
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$var reg 1 d" carry_out $end
|
|
$var reg 1 c" half_c_out $end
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$var reg 1 a" overflow_out $end
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$var reg 8 q" q_out [7:0] $end
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$upscope $end
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|
$scope module l8 $end
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$scope module l8 $end
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$var wire 8 r" a_in [7:0] $end
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$var wire 8 U" a_in [7:0] $end
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$var wire 8 s" b_in [7:0] $end
|
$var wire 8 V" b_in [7:0] $end
|
$var wire 2 t" opcode_in [1:0] $end
|
$var wire 2 W" opcode_in [1:0] $end
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$var reg 8 u" q_out [7:0] $end
|
$var reg 8 X" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module s8 $end
|
$scope module a8 $end
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$var wire 8 v" a_in [7:0] $end
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$var wire 8 Y" a_in [7:0] $end
|
$var wire 8 w" b_in [7:0] $end
|
$var wire 8 Z" b_in [7:0] $end
|
$var wire 1 `" carry_in $end
|
$var wire 1 [" carry $end
|
$var wire 3 x" opcode_in [2:0] $end
|
$var wire 1 8" carry_in $end
|
$var wire 1 S" overflow_in $end
|
$var wire 1 A" half_c_in $end
|
$var wire 1 V" carry_out $end
|
$var wire 2 \" opcode_in [1:0] $end
|
$var reg 1 T" overflow_out $end
|
$var reg 1 ]" carry_out $end
|
$var reg 8 y" q_out [7:0] $end
|
$var reg 1 ^" half_c_out $end
|
|
$var reg 1 _" overflow_out $end
|
|
$var reg 8 `" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
|
$scope module s8 $end
|
|
$var wire 8 a" a_in [7:0] $end
|
|
$var wire 8 b" b_in [7:0] $end
|
|
$var wire 1 8" carry_in $end
|
|
$var wire 1 G" carry_out $end
|
|
$var wire 3 c" opcode_in [2:0] $end
|
|
$var wire 1 J" overflow_in $end
|
|
$var reg 1 d" overflow_out $end
|
|
$var reg 8 e" q_out [7:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_alu $end
|
$scope module alu16 $end
|
$var wire 8 z" opcode [7:0] $end
|
$var wire 8 f" CCR [7:0] $end
|
$var wire 1 i page2_valid $end
|
$var wire 16 g" a_in [15:0] $end
|
$var wire 1 j page3_valid $end
|
$var wire 1 h" arith_c $end
|
$var wire 8 {" postbyte0 [7:0] $end
|
$var wire 16 i" arith_q [15:0] $end
|
$var wire 1 ; dest_flags $end
|
$var wire 1 j" arith_v $end
|
$var reg 5 |" alu_opcode [4:0] $end
|
$var wire 16 k" b_in [15:0] $end
|
$var reg 2 }" dec_alu_right_path_mod [1:0] $end
|
$var wire 1 l" c_in $end
|
|
$var wire 1 - clk_in $end
|
|
$var wire 1 m" n_in $end
|
|
$var wire 5 n" opcode_in [4:0] $end
|
|
$var wire 16 o" q16_mul [15:0] $end
|
|
$var wire 1 p" v_in $end
|
|
$var wire 1 q" z_in $end
|
|
$var reg 4 r" CCRo [3:0] $end
|
|
$var reg 1 s" c16 $end
|
|
$var reg 1 t" n16 $end
|
|
$var reg 16 u" q16 [15:0] $end
|
|
$var reg 16 v" q_out [15:0] $end
|
|
$var reg 1 w" reg_n_in $end
|
|
$var reg 1 x" reg_z_in $end
|
|
$var reg 16 y" regq16 [15:0] $end
|
|
$var reg 1 z" v16 $end
|
|
$var reg 1 {" z16 $end
|
|
$scope module mulu $end
|
|
$var wire 8 |" a [7:0] $end
|
|
$var wire 8 }" b [7:0] $end
|
|
$var wire 1 - clk_in $end
|
|
$var wire 16 ~" q [15:0] $end
|
|
$var reg 16 !# pipe0 [15:0] $end
|
|
$var reg 16 "# pipe1 [15:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_ea $end
|
$scope module a16 $end
|
$var wire 8 ~" eapostbyte [7:0] $end
|
$var wire 16 ## a_in [15:0] $end
|
$var wire 1 H isind $end
|
$var wire 16 $# b_in [15:0] $end
|
$var reg 1 G noofs $end
|
$var wire 1 l" carry_in $end
|
$var reg 1 F ofs16 $end
|
$var wire 2 %# opcode_in [1:0] $end
|
$var reg 1 E ofs8 $end
|
$var reg 1 &# carry_out $end
|
$var reg 1 D write_post $end
|
$var reg 1 '# overflow_out $end
|
|
$var reg 16 (# q_out [15:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_op $end
|
|
$var wire 8 !# opcode [7:0] $end
|
|
$var wire 1 i page2_valid $end
|
|
$var wire 1 j page3_valid $end
|
|
$var wire 8 "# postbyte0 [7:0] $end
|
|
$var wire 4 ## oplo [3:0] $end
|
|
$var reg 3 $# mode [2:0] $end
|
|
$var reg 3 %# optype [2:0] $end
|
|
$var reg 1 &# size $end
|
|
$var reg 1 = use_s $end
|
|
$upscope $end
|
$upscope $end
|
$scope module dec_regs $end
|
|
$var wire 1 ( cpu_clk $end
|
|
$var wire 8 '# opcode [7:0] $end
|
|
$var wire 1 i page2_valid $end
|
|
$var wire 1 j page3_valid $end
|
|
$var wire 8 (# postbyte0 [7:0] $end
|
|
$var wire 1 < write_dest $end
|
|
$var wire 1 > source_size $end
|
|
$var wire 1 K result_size $end
|
|
$var reg 4 )# dest_reg [3:0] $end
|
|
$var reg 4 *# dest_reg_o [3:0] $end
|
|
$var reg 4 +# path_left_addr [3:0] $end
|
|
$var reg 4 ,# path_left_addr_o [3:0] $end
|
|
$var reg 4 -# path_right_addr [3:0] $end
|
|
$var reg 4 .# path_right_addr_o [3:0] $end
|
|
$upscope $end
|
$upscope $end
|
$scope module regs $end
|
$scope module regs $end
|
$var wire 8 /# CCR_in [7:0] $end
|
$var wire 8 )# CCR_in [7:0] $end
|
$var wire 1 W clear_e $end
|
$var wire 8 *# CCR_o [7:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 +# clear_e $end
|
$var wire 16 0# data_w [15:0] $end
|
$var wire 1 - clk_in $end
|
$var wire 1 Z dec_su $end
|
$var wire 16 ,# data_w [15:0] $end
|
$var wire 16 1# eamem_addr_o [15:0] $end
|
$var wire 1 -# dec_su $end
|
$var wire 8 2# eapostbyte [7:0] $end
|
$var wire 16 .# ea_reg_post [15:0] $end
|
$var wire 4 3# exg_dest_r [3:0] $end
|
$var wire 16 /# eamem_addr [15:0] $end
|
$var wire 1 ^ inc_pc $end
|
$var wire 16 0# eamem_addr_o [15:0] $end
|
$var wire 1 _ inc_su $end
|
$var wire 8 1# eapostbyte [7:0] $end
|
$var wire 16 4# new_pc [15:0] $end
|
$var wire 4 2# exg_dest_r [3:0] $end
|
$var wire 16 5# offset16 [15:0] $end
|
$var wire 1 3# inc_pc $end
|
$var wire 4 6# path_left_addr [3:0] $end
|
$var wire 1 4# inc_su $end
|
$var wire 4 7# path_right_addr [3:0] $end
|
$var wire 16 5# left [15:0] $end
|
$var wire 8 8# reg_dp [7:0] $end
|
$var wire 16 6# new_pc [15:0] $end
|
$var wire 16 9# reg_pc [15:0] $end
|
$var wire 16 7# offset16 [15:0] $end
|
$var wire 1 q set_e $end
|
$var wire 4 8# path_left_addr [3:0] $end
|
$var wire 1 = use_s $end
|
$var wire 4 9# path_right_addr [3:0] $end
|
$var wire 1 s write_exg $end
|
$var wire 16 :# pc_plus_1 [15:0] $end
|
$var wire 1 :# write_flags $end
|
$var wire 8 ;# reg_dp [7:0] $end
|
$var wire 1 t write_pc $end
|
$var wire 16 <# reg_pc [15:0] $end
|
$var wire 1 u write_post $end
|
$var wire 16 =# reg_su [15:0] $end
|
$var wire 1 r write_reg $end
|
$var wire 16 ># right [15:0] $end
|
$var wire 4 ;# write_reg_addr [3:0] $end
|
$var wire 4 ?# right_reg [3:0] $end
|
$var wire 1 v write_tfr $end
|
$var wire 1 @# set_e $end
|
$var wire 4 <# right_reg [3:0] $end
|
$var wire 1 I use_s $end
|
$var wire 16 =# right [15:0] $end
|
$var wire 1 A# write_exg $end
|
$var wire 16 ># reg_su [15:0] $end
|
$var wire 1 B# write_flags $end
|
$var wire 16 ?# pc_plus_1 [15:0] $end
|
$var wire 1 C# write_pc $end
|
$var wire 16 @# left [15:0] $end
|
$var wire 1 D# write_post $end
|
$var wire 16 A# eamem_addr [15:0] $end
|
$var wire 1 E# write_reg $end
|
$var wire 16 B# ea_reg_post [15:0] $end
|
$var wire 4 F# write_reg_addr [3:0] $end
|
$var wire 8 C# CCR_o [7:0] $end
|
$var wire 1 G# write_tfr $end
|
$var reg 8 D# ACCA [7:0] $end
|
$var reg 8 H# ACCA [7:0] $end
|
$var reg 8 E# ACCB [7:0] $end
|
$var reg 8 I# ACCB [7:0] $end
|
$var reg 8 F# DP [7:0] $end
|
$var reg 8 J# DP [7:0] $end
|
$var reg 16 G# IX [15:0] $end
|
$var reg 16 K# IX [15:0] $end
|
$var reg 16 H# IY [15:0] $end
|
$var reg 16 L# IY [15:0] $end
|
$var reg 16 I# PC [15:0] $end
|
$var reg 16 M# PC [15:0] $end
|
$var reg 16 J# SS [15:0] $end
|
$var reg 16 N# SS [15:0] $end
|
$var reg 16 K# SU [15:0] $end
|
$var reg 16 O# SU [15:0] $end
|
$var reg 1 L# cff $end
|
$var reg 1 P# cff $end
|
$var reg 1 M# eflag $end
|
$var reg 1 Q# eflag $end
|
$var reg 1 N# fflag $end
|
$var reg 1 R# fflag $end
|
$var reg 1 O# hflag $end
|
$var reg 1 S# hflag $end
|
$var reg 1 P# intff $end
|
$var reg 1 T# intff $end
|
$var reg 1 Q# nff $end
|
$var reg 1 U# nff $end
|
$var reg 16 R# path_left_data [15:0] $end
|
$var reg 16 V# path_left_data [15:0] $end
|
$var reg 16 S# path_right_data [15:0] $end
|
$var reg 16 W# path_right_data [15:0] $end
|
$var reg 1 T# vff $end
|
$var reg 1 X# vff $end
|
$var reg 1 U# zff $end
|
$var reg 1 Y# zff $end
|
$scope module ea $end
|
$scope module ea $end
|
$var wire 8 V# acca [7:0] $end
|
$var wire 8 Z# acca [7:0] $end
|
$var wire 8 W# accb [7:0] $end
|
$var wire 8 [# accb [7:0] $end
|
$var wire 16 X# ea_reg_post_o [15:0] $end
|
$var wire 16 \# ea_reg_post_o [15:0] $end
|
$var wire 16 Y# eamem_addr_o [15:0] $end
|
$var wire 16 ]# eamem_addr_o [15:0] $end
|
$var wire 8 Z# eapostbyte [7:0] $end
|
$var wire 8 ^# eapostbyte [7:0] $end
|
$var wire 16 [# ix [15:0] $end
|
$var wire 16 _# ix [15:0] $end
|
$var wire 16 \# iy [15:0] $end
|
$var wire 16 `# iy [15:0] $end
|
$var wire 16 ]# offset16 [15:0] $end
|
$var wire 16 a# offset16 [15:0] $end
|
$var wire 16 ^# pc [15:0] $end
|
$var wire 16 b# pc [15:0] $end
|
$var wire 16 _# s [15:0] $end
|
$var wire 16 c# s [15:0] $end
|
$var wire 16 `# u [15:0] $end
|
$var wire 16 d# u [15:0] $end
|
$var reg 16 a# ea_reg [15:0] $end
|
$var reg 16 e# ea_reg [15:0] $end
|
$var reg 16 b# ea_reg_post [15:0] $end
|
$var reg 16 f# ea_reg_post [15:0] $end
|
$var reg 16 c# eamem_addr [15:0] $end
|
$var reg 16 g# eamem_addr [15:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope module dec_regs $end
|
|
$var wire 1 - cpu_clk $end
|
|
$var wire 4 h# dest_reg_o [3:0] $end
|
|
$var wire 8 i# opcode [7:0] $end
|
|
$var wire 1 j# page2_valid $end
|
|
$var wire 1 k# page3_valid $end
|
|
$var wire 4 l# path_left_addr_o [3:0] $end
|
|
$var wire 4 m# path_right_addr_o [3:0] $end
|
|
$var wire 8 n# postbyte0 [7:0] $end
|
|
$var wire 1 ; result_size $end
|
|
$var wire 1 H source_size $end
|
|
$var wire 1 J write_dest $end
|
|
$var reg 4 o# dest_reg [3:0] $end
|
|
$var reg 4 p# dest_reg_lo [3:0] $end
|
|
$var reg 4 q# path_left_addr [3:0] $end
|
|
$var reg 4 r# path_left_addr_lo [3:0] $end
|
|
$var reg 4 s# path_right_addr [3:0] $end
|
|
$var reg 4 t# path_right_addr_lo [3:0] $end
|
|
$upscope $end
|
|
$scope module dec_op $end
|
|
$var wire 8 u# opcode [7:0] $end
|
|
$var wire 4 v# oplo [3:0] $end
|
|
$var wire 1 j# page2_valid $end
|
|
$var wire 1 k# page3_valid $end
|
|
$var wire 8 w# postbyte0 [7:0] $end
|
|
$var reg 3 x# mode [2:0] $end
|
|
$var reg 3 y# optype [2:0] $end
|
|
$var reg 1 z# size $end
|
|
$var reg 1 {# use_s $end
|
|
$upscope $end
|
|
$scope module dec_ea $end
|
|
$var wire 8 |# eapostbyte [7:0] $end
|
|
$var wire 1 > isind $end
|
|
$var reg 1 }# noofs $end
|
|
$var reg 1 ~# ofs16 $end
|
|
$var reg 1 !$ ofs8 $end
|
|
$var reg 1 "$ write_post $end
|
$upscope $end
|
$upscope $end
|
|
$scope module dec_alu $end
|
|
$var wire 1 K dest_flags $end
|
|
$var wire 8 #$ opcode [7:0] $end
|
|
$var wire 1 j# page2_valid $end
|
|
$var wire 1 k# page3_valid $end
|
|
$var wire 8 $$ postbyte0 [7:0] $end
|
|
$var reg 5 %$ alu_opcode [4:0] $end
|
|
$var reg 2 &$ dec_alu_right_path_mod [1:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module test_cond $end
|
$scope module test_cond $end
|
$var wire 8 d# CCR [7:0] $end
|
$var wire 8 '$ CCR [7:0] $end
|
$var wire 8 e# opcode [7:0] $end
|
$var wire 8 ($ op [7:0] $end
|
$var wire 1 i page2_valid $end
|
$var wire 8 )$ opcode [7:0] $end
|
$var wire 8 f# postbyte0 [7:0] $end
|
$var wire 1 j# page2_valid $end
|
$var wire 8 g# op [7:0] $end
|
$var wire 8 *$ postbyte0 [7:0] $end
|
$var reg 1 J cond_taken $end
|
$var reg 1 +$ cond_taken $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module imem $end
|
$scope module imem $end
|
$var wire 16 h# addr [15:0] $end
|
$var wire 16 ,$ addr [15:0] $end
|
$var wire 8 i# data_i [7:0] $end
|
$var wire 8 -$ data_i [7:0] $end
|
$var wire 8 j# data_o [7:0] $end
|
$var wire 8 .$ data_o [7:0] $end
|
$var wire 8 k# mem0 [7:0] $end
|
$var wire 8 /$ mem0 [7:0] $end
|
$var wire 8 l# mem1 [7:0] $end
|
$var wire 8 0$ mem1 [7:0] $end
|
$var wire 8 m# mem2 [7:0] $end
|
$var wire 8 1$ mem2 [7:0] $end
|
$var wire 8 n# mem3 [7:0] $end
|
$var wire 8 2$ mem3 [7:0] $end
|
$var wire 1 o# oe $end
|
$var wire 1 3$ oe $end
|
$var wire 1 p# we $end
|
$var wire 1 4$ we $end
|
$var reg 8 q# latecheddata [7:0] $end
|
$var integer 32 5$ i [31:0] $end
|
$var integer 32 r# i [31:0] $end
|
$var reg 8 6$ latecheddata [7:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$enddefinitions $end
|
$enddefinitions $end
|
#0
|
#0
|
$dumpvars
|
$dumpvars
|
b10000000000000000 r#
|
bx 6$
|
|
b10000000000000000 5$
|
|
14$
|
|
13$
|
|
b10100101 2$
|
|
b10100101 1$
|
|
b10100101 0$
|
|
b10100101 /$
|
|
bx .$
|
|
bx -$
|
|
bx ,$
|
|
0+$
|
|
bx *$
|
|
bx )$
|
|
bx ($
|
|
b0 '$
|
|
bx &$
|
|
bx %$
|
|
bx $$
|
|
bx #$
|
|
x"$
|
|
x!$
|
|
x~#
|
|
x}#
|
|
bx |#
|
|
1{#
|
|
0z#
|
|
b110 y#
|
|
b11 x#
|
|
bx w#
|
|
bx v#
|
|
bx u#
|
|
bx t#
|
|
bx s#
|
|
bx r#
|
bx q#
|
bx q#
|
1p#
|
bx p#
|
1o#
|
bx o#
|
b10100101 n#
|
bx n#
|
b10100101 m#
|
bx m#
|
b10100101 l#
|
bx l#
|
b10100101 k#
|
xk#
|
bx j#
|
xj#
|
bx i#
|
bx i#
|
bx h#
|
bx h#
|
bx g#
|
bx g#
|
bx f#
|
bx f#
|
bx e#
|
bx e#
|
b0 d#
|
b111000000000 d#
|
bx c#
|
b111100000000 c#
|
bx b#
|
b1111111111111110 b#
|
bx a#
|
bx a#
|
b111000000000 `#
|
b1010010101011010 `#
|
b111100000000 _#
|
b0 _#
|
b1111111111111110 ^#
|
bx ^#
|
bx ]#
|
bx ]#
|
b1010010101011010 \#
|
bx \#
|
b0 [#
|
bx [#
|
bx Z#
|
bx Z#
|
bx Y#
|
0Y#
|
bx X#
|
0X#
|
bx W#
|
b1111111111111111 W#
|
bx V#
|
b1111111111111111 V#
|
0U#
|
0U#
|
0T#
|
0T#
|
b1111111111111111 S#
|
0S#
|
b1111111111111111 R#
|
0R#
|
0Q#
|
0Q#
|
0P#
|
0P#
|
0O#
|
b111000000000 O#
|
0N#
|
b111100000000 N#
|
0M#
|
b1111111111111110 M#
|
0L#
|
b1010010101011010 L#
|
b111000000000 K#
|
b0 K#
|
b111100000000 J#
|
b0 J#
|
b1111111111111110 I#
|
bx I#
|
b1010010101011010 H#
|
bx H#
|
b0 G#
|
0G#
|
b0 F#
|
bx F#
|
bx E#
|
0E#
|
bx D#
|
xD#
|
b0 C#
|
xC#
|
bx B#
|
0B#
|
bx A#
|
0A#
|
b0 @#
|
x@#
|
b1111111111111111 ?#
|
bx ?#
|
b111x00000000 >#
|
b1111111111111111 >#
|
b1111111111111111 =#
|
b111100000000 =#
|
bx <#
|
b1111111111111110 <#
|
bx ;#
|
b0 ;#
|
0:#
|
b1111111111111111 :#
|
b1111111111111110 9#
|
bx 9#
|
b0 8#
|
bx 8#
|
bx 7#
|
bx 7#
|
bx 6#
|
bx 6#
|
bx 5#
|
b0 5#
|
bx 4#
|
x4#
|
bx 3#
|
x3#
|
bx 2#
|
bx 2#
|
bx 1#
|
bx 1#
|
b0 0#
|
bx 0#
|
b100 /#
|
bx /#
|
bx .#
|
bx .#
|
bx -#
|
x-#
|
bx ,#
|
b0 ,#
|
bx +#
|
x+#
|
bx *#
|
b0 *#
|
bx )#
|
b100 )#
|
bx (#
|
bx (#
|
bx '#
|
x'#
|
x&#
|
x&#
|
bx %#
|
bx %#
|
bx $#
|
bx $#
|
bx ##
|
bx ##
|
bx "#
|
bx "#
|
bx !#
|
bx !#
|
bx ~"
|
bx ~"
|
bx }"
|
bx }"
|
bx |"
|
bx |"
|
bx {"
|
1{"
|
bx z"
|
0z"
|
bx y"
|
bx y"
|
bx x"
|
xx"
|
bx w"
|
xw"
|
bx v"
|
b0 v"
|
bx u"
|
b0 u"
|
bx t"
|
0t"
|
bx s"
|
0s"
|
bx r"
|
b100 r"
|
bx q"
|
0q"
|
0p"
|
0p"
|
bx o"
|
bx o"
|
bx n"
|
bx n"
|
bx m"
|
0m"
|
0l"
|
0l"
|
bx k"
|
bx k"
|
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