| Line 1... |
Line 1... |
$date
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$date
|
Tue Dec 31 08:40:54 2013
|
Wed Jan 1 10:15:21 2014
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$end
|
$end
|
$version
|
$version
|
Icarus Verilog
|
Icarus Verilog
|
$end
|
$end
|
$timescale
|
$timescale
|
| Line 22... |
Line 22... |
$var wire 1 * cpu_firq_n $end
|
$var wire 1 * cpu_firq_n $end
|
$var wire 1 + cpu_irq_n $end
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$var wire 1 + cpu_irq_n $end
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$var wire 1 , cpu_nmi_n $end
|
$var wire 1 , cpu_nmi_n $end
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$var wire 1 ) cpu_reset $end
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$var wire 1 ) cpu_reset $end
|
$var wire 6 - cpu_state_o [5:0] $end
|
$var wire 6 - cpu_state_o [5:0] $end
|
$var wire 1 . k_clk $end
|
$var wire 1 . k_firq_req $end
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$var wire 1 / k_firq_req $end
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$var wire 1 / k_irq_req $end
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$var wire 1 0 k_irq_req $end
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$var wire 1 0 k_nmi_req $end
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$var wire 1 1 k_nmi_req $end
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$var wire 1 1 k_reset $end
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$var wire 1 2 k_reset $end
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$var wire 16 2 regs_o_su [15:0] $end
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$var wire 16 3 regs_o_su [15:0] $end
|
$var wire 16 3 regs_o_right_path_data [15:0] $end
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$var wire 16 4 regs_o_right_path_data [15:0] $end
|
$var wire 16 4 regs_o_pc [15:0] $end
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$var wire 16 5 regs_o_pc [15:0] $end
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$var wire 16 5 regs_o_left_path_data [15:0] $end
|
$var wire 16 6 regs_o_left_path_data [15:0] $end
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$var wire 16 6 regs_o_eamem_addr [15:0] $end
|
$var wire 16 7 regs_o_eamem_addr [15:0] $end
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$var wire 8 7 regs_o_dp [7:0] $end
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$var wire 8 8 regs_o_dp [7:0] $end
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$var wire 8 8 regs_o_CCR [7:0] $end
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$var wire 8 9 regs_o_CCR [7:0] $end
|
$var wire 1 9 dec_o_write_flags $end
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$var wire 1 : dec_o_write_flags $end
|
$var wire 1 : dec_o_wdest $end
|
$var wire 1 ; dec_o_wdest $end
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$var wire 1 ; dec_o_use_s $end
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$var wire 1 < dec_o_use_s $end
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$var wire 1 < dec_o_source_size $end
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$var wire 1 = dec_o_source_size $end
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$var wire 2 = dec_o_right_path_mod [1:0] $end
|
$var wire 2 > dec_o_right_path_mod [1:0] $end
|
$var wire 4 > dec_o_right_path_addr [3:0] $end
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$var wire 4 ? dec_o_right_path_addr [3:0] $end
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$var wire 3 ? dec_o_p1_optype [2:0] $end
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$var wire 3 @ dec_o_p1_optype [2:0] $end
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$var wire 3 @ dec_o_p1_mode [2:0] $end
|
$var wire 3 A dec_o_p1_mode [2:0] $end
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$var wire 4 A dec_o_left_path_addr [3:0] $end
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$var wire 4 B dec_o_left_path_addr [3:0] $end
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$var wire 1 B dec_o_ea_wpost $end
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$var wire 1 C dec_o_ea_wpost $end
|
$var wire 1 C dec_o_ea_ofs8 $end
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$var wire 1 D dec_o_ea_ofs8 $end
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$var wire 1 D dec_o_ea_ofs16 $end
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$var wire 1 E dec_o_ea_ofs16 $end
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$var wire 1 E dec_o_ea_ofs0 $end
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$var wire 1 F dec_o_ea_ofs0 $end
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$var wire 1 F dec_o_ea_indirect $end
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$var wire 1 G dec_o_ea_indirect $end
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$var wire 4 G dec_o_dest_reg_addr [3:0] $end
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$var wire 4 H dec_o_dest_reg_addr [3:0] $end
|
$var wire 1 H dec_o_cond_taken $end
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$var wire 1 I dec_o_cond_taken $end
|
$var wire 1 I dec_o_alu_size $end
|
$var wire 1 J dec_o_alu_size $end
|
$var wire 5 J dec_o_alu_opcode [4:0] $end
|
$var wire 5 K dec_o_alu_opcode [4:0] $end
|
|
$var wire 1 # cpu_we_o $end
|
$var wire 1 # cpu_we_o $end
|
$var wire 1 $ cpu_oe_o $end
|
$var wire 1 $ cpu_oe_o $end
|
$var wire 8 L cpu_data_o [7:0] $end
|
$var wire 8 K cpu_data_o [7:0] $end
|
$var wire 8 M cpu_data_i [7:0] $end
|
$var wire 8 L cpu_data_i [7:0] $end
|
$var wire 16 N cpu_addr_o [15:0] $end
|
$var wire 16 M cpu_addr_o [15:0] $end
|
$var wire 16 O alu_o_result [15:0] $end
|
$var wire 16 N alu_o_result [15:0] $end
|
$var wire 8 P alu_o_CCR [7:0] $end
|
$var wire 8 O alu_o_CCR [7:0] $end
|
$var reg 4 Q datamux_o_alu_in_left_path_addr [3:0] $end
|
$var reg 4 P datamux_o_alu_in_left_path_addr [3:0] $end
|
$var reg 16 R datamux_o_alu_in_left_path_data [15:0] $end
|
$var reg 16 Q datamux_o_alu_in_left_path_data [15:0] $end
|
$var reg 16 S datamux_o_alu_in_right_path_data [15:0] $end
|
$var reg 16 R datamux_o_alu_in_right_path_data [15:0] $end
|
$var reg 16 T datamux_o_dest [15:0] $end
|
$var reg 16 S datamux_o_dest [15:0] $end
|
$var reg 4 U datamux_o_dest_reg_addr [3:0] $end
|
$var reg 4 T datamux_o_dest_reg_addr [3:0] $end
|
$var reg 1 V k_clear_e $end
|
$var reg 1 U k_clear_e $end
|
$var reg 16 W k_cpu_addr [15:0] $end
|
$var reg 16 V k_cpu_addr [15:0] $end
|
$var reg 8 X k_cpu_data_o [7:0] $end
|
$var reg 8 W k_cpu_data_o [7:0] $end
|
$var reg 1 $ k_cpu_oe $end
|
$var reg 1 $ k_cpu_oe $end
|
$var reg 1 # k_cpu_we $end
|
$var reg 1 # k_cpu_we $end
|
$var reg 1 Y k_dec_su $end
|
$var reg 1 X k_dec_su $end
|
$var reg 8 Z k_eahi [7:0] $end
|
$var reg 8 Y k_eahi [7:0] $end
|
$var reg 8 [ k_ealo [7:0] $end
|
$var reg 8 Z k_ealo [7:0] $end
|
$var reg 1 \ k_forced_mem_size $end
|
$var reg 1 [ k_forced_mem_size $end
|
$var reg 1 ] k_inc_pc $end
|
$var reg 1 \ k_inc_pc $end
|
$var reg 1 ^ k_inc_su $end
|
$var reg 1 ] k_inc_su $end
|
$var reg 8 _ k_ind_ea [7:0] $end
|
$var reg 8 ^ k_ind_ea [7:0] $end
|
$var reg 2 ` k_mem_dest [1:0] $end
|
$var reg 2 _ k_mem_dest [1:0] $end
|
$var reg 8 a k_memhi [7:0] $end
|
$var reg 8 ` k_memhi [7:0] $end
|
$var reg 8 b k_memlo [7:0] $end
|
$var reg 8 a k_memlo [7:0] $end
|
|
$var reg 1 b k_mul_cnt $end
|
$var reg 16 c k_new_pc [15:0] $end
|
$var reg 16 c k_new_pc [15:0] $end
|
$var reg 8 d k_ofshi [7:0] $end
|
$var reg 8 d k_ofshi [7:0] $end
|
$var reg 8 e k_ofslo [7:0] $end
|
$var reg 8 e k_ofslo [7:0] $end
|
$var reg 8 f k_opcode [7:0] $end
|
$var reg 8 f k_opcode [7:0] $end
|
$var reg 1 g k_p2_valid $end
|
$var reg 1 g k_p2_valid $end
|
| Line 103... |
Line 103... |
$var reg 6 v next_push_state [5:0] $end
|
$var reg 6 v next_push_state [5:0] $end
|
$var reg 6 w next_state [5:0] $end
|
$var reg 6 w next_state [5:0] $end
|
$var reg 6 x state [5:0] $end
|
$var reg 6 x state [5:0] $end
|
$scope module alu $end
|
$scope module alu $end
|
$var wire 16 y a_in [15:0] $end
|
$var wire 16 y a_in [15:0] $end
|
$var wire 16 z and16_r [15:0] $end
|
$var wire 16 z b_in [15:0] $end
|
$var wire 16 { and16_w [15:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 8 | and8_r [7:0] $end
|
$var wire 1 I sz_in $end
|
$var wire 8 } and8_w [7:0] $end
|
$var wire 8 { q8_out [7:0] $end
|
$var wire 16 ~ asr16_r [15:0] $end
|
$var wire 16 | q16_out [15:0] $end
|
$var wire 8 !" asr8_r [7:0] $end
|
$var wire 5 } opcode_in [4:0] $end
|
$var wire 16 "" b_in [15:0] $end
|
$var wire 8 ~ ccr8_out [7:0] $end
|
$var wire 1 #" cand16_r $end
|
$var wire 4 !" ccr16_out [3:0] $end
|
$var wire 1 $" cand8_r $end
|
$var wire 8 "" CCR [7:0] $end
|
$var wire 1 . clk $end
|
$var reg 8 #" CCRo [7:0] $end
|
$var wire 1 %" cneg16_r $end
|
$var reg 16 $" q_out [15:0] $end
|
$var wire 1 &" cneg8_r $end
|
$var reg 16 %" ra_in [15:0] $end
|
$var wire 16 '" com16_r [15:0] $end
|
$var reg 16 &" rb_in [15:0] $end
|
$var wire 16 (" com16_w [15:0] $end
|
$scope module alu16 $end
|
$var wire 8 )" com8_r [7:0] $end
|
$var wire 16 '" a_in [15:0] $end
|
$var wire 8 *" com8_w [7:0] $end
|
$var wire 16 (" and16_r [15:0] $end
|
$var wire 16 +" eor16_r [15:0] $end
|
$var wire 16 )" and16_w [15:0] $end
|
$var wire 16 ," eor16_w [15:0] $end
|
$var wire 16 *" asr16_r [15:0] $end
|
$var wire 8 -" eor8_r [7:0] $end
|
$var wire 16 +" b_in [15:0] $end
|
$var wire 8 ." eor8_w [7:0] $end
|
$var wire 1 ," cand16_r $end
|
$var wire 16 /" mul16_r [15:0] $end
|
$var wire 1 ( clk_in $end
|
$var wire 16 0" neg16_r [15:0] $end
|
$var wire 1 -" cneg16_r $end
|
$var wire 8 1" neg8_r [7:0] $end
|
$var wire 16 ." com16_r [15:0] $end
|
$var wire 16 2" or16_r [15:0] $end
|
$var wire 16 /" com16_w [15:0] $end
|
$var wire 16 3" or16_w [15:0] $end
|
$var wire 16 0" eor16_r [15:0] $end
|
$var wire 8 4" or8_r [7:0] $end
|
$var wire 16 1" eor16_w [15:0] $end
|
$var wire 8 5" or8_w [7:0] $end
|
$var wire 16 2" neg16_r [15:0] $end
|
$var wire 16 6" rol16_r [15:0] $end
|
$var wire 16 3" or16_r [15:0] $end
|
$var wire 8 7" rol8_r [7:0] $end
|
$var wire 16 4" or16_w [15:0] $end
|
$var wire 16 8" ror16_r [15:0] $end
|
$var wire 16 5" rol16_r [15:0] $end
|
$var wire 8 9" ror8_r [7:0] $end
|
$var wire 16 6" ror16_r [15:0] $end
|
$var wire 16 :" shl16_r [15:0] $end
|
$var wire 16 7" shl16_r [15:0] $end
|
$var wire 8 ;" shl8_r [7:0] $end
|
$var wire 16 8" shr16_r [15:0] $end
|
$var wire 16 <" shr16_r [15:0] $end
|
$var wire 1 9" vadc16_r $end
|
$var wire 8 =" shr8_r [7:0] $end
|
$var wire 1 :" vadd16_r $end
|
$var wire 1 >" vadc16_r $end
|
$var wire 1 ;" vand16_r $end
|
$var wire 1 ?" vadc8_r $end
|
$var wire 1 <" vasr16_r $end
|
$var wire 1 @" vadd16_r $end
|
$var wire 1 =" vcom16_r $end
|
$var wire 1 A" vadd8_r $end
|
$var wire 1 >" vneg16_r $end
|
$var wire 1 B" vand16_r $end
|
$var wire 1 ?" vrol16_r $end
|
$var wire 1 C" vand8_r $end
|
$var wire 1 @" vror16_r $end
|
$var wire 1 D" vasr16_r $end
|
$var wire 1 A" vsbc16_r $end
|
$var wire 1 E" vasr8_r $end
|
$var wire 1 B" vshl16_r $end
|
$var wire 1 F" vcom16_r $end
|
$var wire 1 C" vshr16_r $end
|
$var wire 1 G" vcom8_r $end
|
$var wire 1 D" vsub16_r $end
|
$var wire 1 H" vneg16_r $end
|
$var wire 1 E" z_in $end
|
$var wire 1 I" vneg8_r $end
|
$var wire 1 F" v_in $end
|
$var wire 1 J" vrol16_r $end
|
$var wire 16 G" sub16_w [15:0] $end
|
$var wire 1 K" vrol8_r $end
|
$var wire 16 H" sub16_r [15:0] $end
|
$var wire 1 L" vror16_r $end
|
$var wire 16 I" shr16_w [15:0] $end
|
$var wire 1 M" vror8_r $end
|
$var wire 16 J" shl16_w [15:0] $end
|
$var wire 1 N" vsbc16_r $end
|
$var wire 16 K" sbc16_w [15:0] $end
|
$var wire 1 O" vsbc8_r $end
|
$var wire 16 L" sbc16_r [15:0] $end
|
$var wire 1 P" vshl16_r $end
|
$var wire 16 M" ror16_w [15:0] $end
|
$var wire 1 Q" vshl8_r $end
|
$var wire 16 N" rol16_w [15:0] $end
|
$var wire 1 R" vshr16_r $end
|
$var wire 5 O" opcode_in [4:0] $end
|
$var wire 1 S" vshr8_r $end
|
$var wire 16 P" neg16_w [15:0] $end
|
$var wire 1 T" vsub16_r $end
|
$var wire 1 Q" n_in $end
|
$var wire 1 U" vsub8_r $end
|
$var wire 16 R" mul16_r [15:0] $end
|
$var wire 1 V" z_in $end
|
$var wire 1 S" csub16_w $end
|
$var wire 1 W" v_in $end
|
$var wire 1 T" csub16_r $end
|
$var wire 1 J sz_in $end
|
$var wire 1 U" cshr16_r $end
|
$var wire 8 X" sub8_w [7:0] $end
|
$var wire 1 V" cshl16_r $end
|
$var wire 8 Y" sub8_r [7:0] $end
|
$var wire 1 W" csbc16_w $end
|
$var wire 16 Z" sub16_w [15:0] $end
|
$var wire 1 X" csbc16_r $end
|
$var wire 16 [" sub16_r [15:0] $end
|
$var wire 1 Y" cror16_r $end
|
$var wire 8 \" shr8_w [7:0] $end
|
$var wire 1 Z" crol16_r $end
|
$var wire 16 ]" shr16_w [15:0] $end
|
$var wire 1 [" cmul16_r $end
|
$var wire 8 ^" shl8_w [7:0] $end
|
$var wire 1 \" ccom16_r $end
|
$var wire 16 _" shl16_w [15:0] $end
|
$var wire 1 ]" casr16_r $end
|
$var wire 8 `" sbc8_w [7:0] $end
|
$var wire 1 ^" cadd16_w $end
|
$var wire 8 a" sbc8_r [7:0] $end
|
$var wire 1 _" cadd16_r $end
|
$var wire 16 b" sbc16_w [15:0] $end
|
$var wire 1 `" cadc16_w $end
|
$var wire 16 c" sbc16_r [15:0] $end
|
$var wire 1 a" cadc16_r $end
|
$var wire 8 d" ror8_w [7:0] $end
|
$var wire 1 b" c_in $end
|
$var wire 16 e" ror16_w [15:0] $end
|
$var wire 16 c" asr16_w [15:0] $end
|
$var wire 8 f" rol8_w [7:0] $end
|
$var wire 16 d" add16_w [15:0] $end
|
$var wire 16 g" rol16_w [15:0] $end
|
$var wire 16 e" add16_r [15:0] $end
|
$var wire 5 h" opcode_in [4:0] $end
|
$var wire 16 f" adc16_w [15:0] $end
|
$var wire 8 i" neg8_w [7:0] $end
|
$var wire 16 g" adc16_r [15:0] $end
|
$var wire 16 j" neg16_w [15:0] $end
|
$var wire 8 h" CCR [7:0] $end
|
$var wire 1 k" n_in $end
|
$var reg 4 i" CCRo [3:0] $end
|
$var wire 16 l" mul16_w [15:0] $end
|
$var reg 1 j" c16 $end
|
$var wire 1 m" h_in $end
|
$var reg 1 k" n16 $end
|
$var wire 1 n" daa_lnm9 $end
|
$var reg 16 l" q16 [15:0] $end
|
$var wire 4 o" daa8l_r [3:0] $end
|
$var reg 16 m" q_out [15:0] $end
|
$var wire 4 p" daa8h_r [3:0] $end
|
$var reg 1 n" reg_n_in $end
|
$var wire 1 q" csub8_w $end
|
$var reg 1 o" reg_z_in $end
|
$var wire 1 r" csub8_r $end
|
$var reg 16 p" regq16 [15:0] $end
|
$var wire 1 s" csub16_w $end
|
$var reg 1 q" v16 $end
|
$var wire 1 t" csub16_r $end
|
$var reg 1 r" z16 $end
|
$var wire 1 u" cshr8_r $end
|
$scope module mulu $end
|
$var wire 1 v" cshr16_r $end
|
$var wire 8 s" a [7:0] $end
|
$var wire 1 w" cshl8_r $end
|
$var wire 8 t" b [7:0] $end
|
$var wire 1 x" cshl16_r $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 y" csbc8_w $end
|
$var wire 16 u" q [15:0] $end
|
$var wire 1 z" csbc8_r $end
|
$var reg 16 v" pipe0 [15:0] $end
|
$var wire 1 {" csbc16_w $end
|
$var reg 16 w" pipe1 [15:0] $end
|
$var wire 1 |" csbc16_r $end
|
$upscope $end
|
$var wire 1 }" cror8_r $end
|
$upscope $end
|
$var wire 1 ~" cror16_r $end
|
$scope module alu8 $end
|
$var wire 1 !# crol8_r $end
|
$var wire 16 x" a_in [15:0] $end
|
$var wire 1 "# crol16_r $end
|
$var wire 8 y" and8_r [7:0] $end
|
$var wire 1 ## cmul16_r $end
|
$var wire 8 z" and8_w [7:0] $end
|
$var wire 1 $# cdaa8_r $end
|
$var wire 8 {" asr8_r [7:0] $end
|
$var wire 1 %# ccom8_r $end
|
$var wire 16 |" b_in [15:0] $end
|
$var wire 1 &# ccom16_r $end
|
$var wire 1 }" cand8_r $end
|
$var wire 1 '# casr8_r $end
|
$var wire 1 ( clk_in $end
|
$var wire 1 (# casr16_r $end
|
$var wire 1 ~" cneg8_r $end
|
$var wire 1 )# cadd8_w $end
|
$var wire 8 !# com8_r [7:0] $end
|
$var wire 1 *# cadd8_r $end
|
$var wire 8 "# com8_w [7:0] $end
|
$var wire 1 +# cadd16_w $end
|
$var wire 8 ## eor8_r [7:0] $end
|
$var wire 1 ,# cadd16_r $end
|
$var wire 8 $# eor8_w [7:0] $end
|
$var wire 1 -# cadc8_w $end
|
$var wire 8 %# neg8_r [7:0] $end
|
$var wire 1 .# cadc8_r $end
|
$var wire 8 &# or8_r [7:0] $end
|
$var wire 1 /# cadc16_w $end
|
$var wire 8 '# or8_w [7:0] $end
|
$var wire 1 0# cadc16_r $end
|
$var wire 8 (# rol8_r [7:0] $end
|
$var wire 1 1# c_in $end
|
$var wire 8 )# ror8_r [7:0] $end
|
$var wire 8 2# asr8_w [7:0] $end
|
$var wire 8 *# shl8_r [7:0] $end
|
$var wire 16 3# asr16_w [15:0] $end
|
$var wire 8 +# shr8_r [7:0] $end
|
$var wire 8 4# add8_w [7:0] $end
|
$var wire 1 ,# vadc8_r $end
|
$var wire 8 5# add8_r [7:0] $end
|
$var wire 1 -# vadd8_r $end
|
$var wire 16 6# add16_w [15:0] $end
|
$var wire 1 .# vand8_r $end
|
$var wire 16 7# add16_r [15:0] $end
|
$var wire 1 /# vasr8_r $end
|
$var wire 8 8# adc8_w [7:0] $end
|
$var wire 1 0# vcom8_r $end
|
$var wire 8 9# adc8_r [7:0] $end
|
$var wire 1 1# vneg8_r $end
|
$var wire 16 :# adc16_w [15:0] $end
|
$var wire 1 2# vrol8_r $end
|
$var wire 16 ;# adc16_r [15:0] $end
|
$var wire 1 3# vror8_r $end
|
$var wire 8 <# CCR [7:0] $end
|
$var wire 1 4# vsbc8_r $end
|
$var reg 8 =# CCRo [7:0] $end
|
$var wire 1 5# vshl8_r $end
|
$var reg 1 ># c16 $end
|
$var wire 1 6# vshr8_r $end
|
$var reg 1 ?# c8 $end
|
$var wire 1 7# vsub8_r $end
|
$var reg 1 @# h8 $end
|
$var wire 1 8# z_in $end
|
$var reg 1 A# n16 $end
|
$var wire 1 9# v_in $end
|
$var reg 1 B# n8 $end
|
$var wire 8 :# sub8_w [7:0] $end
|
$var reg 16 C# q16 [15:0] $end
|
$var wire 8 ;# sub8_r [7:0] $end
|
$var reg 8 D# q8 [7:0] $end
|
$var wire 8 <# shr8_w [7:0] $end
|
$var reg 16 E# q_out [15:0] $end
|
$var wire 8 =# shl8_w [7:0] $end
|
$var reg 1 F# reg_n_in $end
|
$var wire 8 ># sbc8_w [7:0] $end
|
$var reg 1 G# reg_z_in $end
|
$var wire 8 ?# sbc8_r [7:0] $end
|
$var reg 16 H# regq16 [15:0] $end
|
$var wire 8 @# ror8_w [7:0] $end
|
$var reg 8 I# regq8 [7:0] $end
|
$var wire 8 A# rol8_w [7:0] $end
|
$var reg 1 J# v16 $end
|
$var wire 5 B# opcode_in [4:0] $end
|
$var reg 1 K# v8 $end
|
$var wire 8 C# neg8_w [7:0] $end
|
$var reg 1 L# z16 $end
|
$var wire 1 D# n_in $end
|
$var reg 1 M# z8 $end
|
$var wire 1 E# h_in $end
|
|
$var wire 1 F# daa_lnm9 $end
|
|
$var wire 4 G# daa8l_r [3:0] $end
|
|
$var wire 4 H# daa8h_r [3:0] $end
|
|
$var wire 1 I# csub8_w $end
|
|
$var wire 1 J# csub8_r $end
|
|
$var wire 1 K# cshr8_r $end
|
|
$var wire 1 L# cshl8_r $end
|
|
$var wire 1 M# csbc8_w $end
|
|
$var wire 1 N# csbc8_r $end
|
|
$var wire 1 O# cror8_r $end
|
|
$var wire 1 P# crol8_r $end
|
|
$var wire 1 Q# cdaa8_r $end
|
|
$var wire 1 R# ccom8_r $end
|
|
$var wire 1 S# casr8_r $end
|
|
$var wire 1 T# cadd8_w $end
|
|
$var wire 1 U# cadd8_r $end
|
|
$var wire 1 V# cadc8_w $end
|
|
$var wire 1 W# cadc8_r $end
|
|
$var wire 1 X# c_in $end
|
|
$var wire 8 Y# asr8_w [7:0] $end
|
|
$var wire 8 Z# add8_w [7:0] $end
|
|
$var wire 8 [# add8_r [7:0] $end
|
|
$var wire 8 \# adc8_w [7:0] $end
|
|
$var wire 8 ]# adc8_r [7:0] $end
|
|
$var wire 8 ^# CCR [7:0] $end
|
|
$var reg 8 _# CCRo [7:0] $end
|
|
$var reg 1 `# c8 $end
|
|
$var reg 1 a# h8 $end
|
|
$var reg 8 b# q8 [7:0] $end
|
|
$var reg 8 c# q_out [7:0] $end
|
|
$var reg 8 d# regq8 [7:0] $end
|
|
$var reg 1 e# v8 $end
|
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_alu $end
|
$scope module dec_alu $end
|
$var wire 8 N# opcode [7:0] $end
|
$var wire 8 f# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 8 O# postbyte0 [7:0] $end
|
$var wire 8 g# postbyte0 [7:0] $end
|
$var wire 1 : dest_flags $end
|
$var wire 1 9 dest_flags $end
|
$var reg 5 P# alu_opcode [4:0] $end
|
$var reg 5 h# alu_opcode [4:0] $end
|
$var reg 2 Q# dec_alu_right_path_mod [1:0] $end
|
$var reg 2 i# dec_alu_right_path_mod [1:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_ea $end
|
$scope module dec_ea $end
|
$var wire 8 R# eapostbyte [7:0] $end
|
$var wire 8 j# eapostbyte [7:0] $end
|
$var wire 1 G isind $end
|
$var wire 1 F isind $end
|
$var reg 1 F noofs $end
|
$var reg 1 E noofs $end
|
$var reg 1 E ofs16 $end
|
$var reg 1 D ofs16 $end
|
$var reg 1 D ofs8 $end
|
$var reg 1 C ofs8 $end
|
$var reg 1 C write_post $end
|
$var reg 1 B write_post $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_op $end
|
$scope module dec_op $end
|
$var wire 8 S# opcode [7:0] $end
|
$var wire 8 k# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 8 T# postbyte0 [7:0] $end
|
$var wire 8 l# postbyte0 [7:0] $end
|
$var wire 4 U# oplo [3:0] $end
|
$var wire 4 m# oplo [3:0] $end
|
$var reg 3 V# mode [2:0] $end
|
$var reg 3 n# mode [2:0] $end
|
$var reg 3 W# optype [2:0] $end
|
$var reg 3 o# optype [2:0] $end
|
$var reg 1 X# size $end
|
$var reg 1 p# size $end
|
$var reg 1 < use_s $end
|
$var reg 1 ; use_s $end
|
$upscope $end
|
$upscope $end
|
$scope module dec_regs $end
|
$scope module dec_regs $end
|
$var wire 8 Y# opcode [7:0] $end
|
$var wire 8 q# opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 1 h page3_valid $end
|
$var wire 8 Z# postbyte0 [7:0] $end
|
$var wire 8 r# postbyte0 [7:0] $end
|
$var wire 1 ; write_dest $end
|
$var wire 1 : write_dest $end
|
$var wire 1 = source_size $end
|
$var wire 1 < source_size $end
|
$var wire 1 J result_size $end
|
$var wire 1 I result_size $end
|
$var reg 4 [# dest_reg [3:0] $end
|
$var reg 4 s# dest_reg [3:0] $end
|
$var reg 4 \# path_left_addr [3:0] $end
|
$var reg 4 t# path_left_addr [3:0] $end
|
$var reg 4 ]# path_right_addr [3:0] $end
|
$var reg 4 u# path_right_addr [3:0] $end
|
$upscope $end
|
$upscope $end
|
$scope module regs $end
|
$scope module regs $end
|
$var wire 8 ^# CCR_in [7:0] $end
|
$var wire 8 v# CCR_in [7:0] $end
|
$var wire 1 V clear_e $end
|
$var wire 1 U clear_e $end
|
$var wire 1 . clk_in $end
|
$var wire 1 ( clk_in $end
|
$var wire 16 _# data_w [15:0] $end
|
$var wire 16 w# data_w [15:0] $end
|
$var wire 1 Y dec_su $end
|
$var wire 1 X dec_su $end
|
$var wire 8 `# eapostbyte [7:0] $end
|
$var wire 8 x# eapostbyte [7:0] $end
|
$var wire 4 a# exg_dest_r [3:0] $end
|
$var wire 4 y# exg_dest_r [3:0] $end
|
$var wire 1 ] inc_pc $end
|
$var wire 1 \ inc_pc $end
|
$var wire 1 ^ inc_su $end
|
$var wire 1 ] inc_su $end
|
$var wire 16 b# new_pc [15:0] $end
|
$var wire 16 z# new_pc [15:0] $end
|
$var wire 16 c# offset16 [15:0] $end
|
$var wire 16 {# offset16 [15:0] $end
|
$var wire 4 d# path_left_addr [3:0] $end
|
$var wire 4 |# path_left_addr [3:0] $end
|
$var wire 4 e# path_right_addr [3:0] $end
|
$var wire 4 }# path_right_addr [3:0] $end
|
$var wire 8 f# reg_dp [7:0] $end
|
$var wire 8 ~# reg_dp [7:0] $end
|
$var wire 16 g# reg_pc [15:0] $end
|
$var wire 16 !$ reg_pc [15:0] $end
|
$var wire 1 o set_e $end
|
$var wire 1 o set_e $end
|
$var wire 1 < use_s $end
|
$var wire 1 ; use_s $end
|
$var wire 1 q write_exg $end
|
$var wire 1 q write_exg $end
|
$var wire 1 h# write_flags $end
|
$var wire 1 "$ write_flags $end
|
$var wire 1 r write_pc $end
|
$var wire 1 r write_pc $end
|
$var wire 1 s write_post $end
|
$var wire 1 s write_post $end
|
$var wire 1 p write_reg $end
|
$var wire 1 p write_reg $end
|
$var wire 4 i# write_reg_addr [3:0] $end
|
$var wire 4 #$ write_reg_addr [3:0] $end
|
$var wire 1 t write_tfr $end
|
$var wire 1 t write_tfr $end
|
$var wire 16 j# u_plus_1 [15:0] $end
|
$var wire 16 $$ reg_su [15:0] $end
|
$var wire 16 k# u_minus_1 [15:0] $end
|
$var wire 16 %$ left [15:0] $end
|
$var wire 16 l# s_plus_1 [15:0] $end
|
$var wire 8 &$ CCR_o [7:0] $end
|
$var wire 16 m# s_minus_1 [15:0] $end
|
$var reg 8 '$ ACCA [7:0] $end
|
$var wire 16 n# reg_su [15:0] $end
|
$var reg 8 ($ ACCB [7:0] $end
|
$var wire 16 o# pc_plus_1 [15:0] $end
|
$var reg 8 )$ DP [7:0] $end
|
$var wire 16 p# new_u [15:0] $end
|
$var reg 16 *$ IX [15:0] $end
|
$var wire 16 q# new_s [15:0] $end
|
$var reg 16 +$ IY [15:0] $end
|
$var wire 16 r# left [15:0] $end
|
$var reg 16 ,$ PC [15:0] $end
|
$var wire 8 s# CCR_o [7:0] $end
|
$var reg 16 -$ SS [15:0] $end
|
$var reg 8 t# ACCA [7:0] $end
|
$var reg 16 .$ SU [15:0] $end
|
$var reg 8 u# ACCB [7:0] $end
|
$var reg 1 /$ cff $end
|
$var reg 8 v# DP [7:0] $end
|
$var reg 16 0$ ea_reg [15:0] $end
|
$var reg 16 w# IX [15:0] $end
|
$var reg 16 1$ ea_reg_post [15:0] $end
|
$var reg 16 x# IY [15:0] $end
|
$var reg 16 2$ eamem_addr [15:0] $end
|
$var reg 16 y# PC [15:0] $end
|
$var reg 1 3$ eflag $end
|
$var reg 16 z# SS [15:0] $end
|
$var reg 1 4$ fflag $end
|
$var reg 16 {# SU [15:0] $end
|
$var reg 1 5$ hflag $end
|
$var reg 1 |# cff $end
|
$var reg 1 6$ intff $end
|
$var reg 16 }# ea_reg [15:0] $end
|
$var reg 1 7$ nff $end
|
$var reg 16 ~# ea_reg_post [15:0] $end
|
$var reg 16 8$ path_left_data [15:0] $end
|
$var reg 16 !$ eamem_addr [15:0] $end
|
$var reg 16 9$ path_right_data [15:0] $end
|
$var reg 1 "$ eflag $end
|
$var reg 1 :$ vff $end
|
$var reg 1 #$ fflag $end
|
$var reg 1 ;$ zff $end
|
$var reg 1 $$ hflag $end
|
|
$var reg 1 %$ intff $end
|
|
$var reg 1 &$ nff $end
|
|
$var reg 16 '$ path_left_data [15:0] $end
|
|
$var reg 16 ($ path_right_data [15:0] $end
|
|
$var reg 1 )$ vff $end
|
|
$var reg 1 *$ zff $end
|
|
$upscope $end
|
$upscope $end
|
$scope module test_cond $end
|
$scope module test_cond $end
|
$var wire 8 +$ CCR [7:0] $end
|
$var wire 8 <$ CCR [7:0] $end
|
$var wire 8 ,$ opcode [7:0] $end
|
$var wire 8 =$ opcode [7:0] $end
|
$var wire 1 g page2_valid $end
|
$var wire 1 g page2_valid $end
|
$var wire 8 -$ postbyte0 [7:0] $end
|
$var wire 8 >$ postbyte0 [7:0] $end
|
$var wire 8 .$ op [7:0] $end
|
$var wire 8 ?$ op [7:0] $end
|
$var reg 1 I cond_taken $end
|
$var reg 1 H cond_taken $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$scope module imem $end
|
$scope module imem $end
|
$var wire 16 /$ addr [15:0] $end
|
$var wire 16 @$ addr [15:0] $end
|
$var wire 8 0$ data_i [7:0] $end
|
$var wire 8 A$ data_i [7:0] $end
|
$var wire 8 1$ data_o [7:0] $end
|
$var wire 8 B$ data_o [7:0] $end
|
$var wire 8 2$ mem0 [7:0] $end
|
$var wire 8 C$ mem0 [7:0] $end
|
$var wire 8 3$ mem1 [7:0] $end
|
$var wire 8 D$ mem1 [7:0] $end
|
$var wire 8 4$ mem2 [7:0] $end
|
$var wire 8 E$ mem2 [7:0] $end
|
$var wire 8 5$ mem3 [7:0] $end
|
$var wire 8 F$ mem3 [7:0] $end
|
$var wire 1 6$ oe $end
|
$var wire 1 G$ oe $end
|
$var wire 1 7$ we $end
|
$var wire 1 H$ we $end
|
$var reg 8 8$ latecheddata [7:0] $end
|
$var reg 8 I$ latecheddata [7:0] $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$upscope $end
|
$enddefinitions $end
|
$enddefinitions $end
|
#0
|
#0
|
$dumpvars
|
$dumpvars
|
bx 8$
|
bx I$
|
17$
|
1H$
|
16$
|
1G$
|
b10001110 5$
|
b111101 F$
|
b10111011 4$
|
b10111011 E$
|
b10101010 3$
|
b10101010 D$
|
b11001100 2$
|
b11001100 C$
|
|
bx B$
|
|
bx A$
|
|
bx @$
|
|
bx ?$
|
|
bx >$
|
|
bx =$
|
|
b0 <$
|
|
0;$
|
|
0:$
|
|
b1111111111111111 9$
|
|
b1111111111111111 8$
|
|
07$
|
|
06$
|
|
05$
|
|
04$
|
|
03$
|
|
bx 2$
|
bx 1$
|
bx 1$
|
bx 0$
|
bx 0$
|
bx /$
|
0/$
|
bx .$
|
b111000000000 .$
|
bx -$
|
b111100000000 -$
|
bx ,$
|
b1111111111111110 ,$
|
b0 +$
|
b1010010101011010 +$
|
0*$
|
b0 *$
|
0)$
|
b0 )$
|
b1111111111111111 ($
|
bx ($
|
b1111111111111111 '$
|
bx '$
|
0&$
|
b0 &$
|
0%$
|
b0 %$
|
0$$
|
b111x00000000 $$
|
0#$
|
bx #$
|
0"$
|
0"$
|
bx !$
|
b1111111111111110 !$
|
bx ~#
|
b0 ~#
|
bx }#
|
bx }#
|
0|#
|
bx |#
|
b111000000000 {#
|
bx {#
|
b111100000000 z#
|
bx z#
|
b1111111111111110 y#
|
bx y#
|
b1010010101011010 x#
|
bx x#
|
b0 w#
|
b0 w#
|
b0 v#
|
b100 v#
|
bx u#
|
bx u#
|
bx t#
|
bx t#
|
b0 s#
|
bx s#
|
bx r#
|
bx r#
|
bx q#
|
bx q#
|
bx p#
|
xp#
|
b1111111111111111 o#
|
bx o#
|
b111x00000000 n#
|
bx n#
|
b111011111111 m#
|
bx m#
|
b111100000001 l#
|
bx l#
|
b110111111111 k#
|
bx k#
|
b111000000001 j#
|
bx j#
|
bx i#
|
bx i#
|
0h#
|
bx h#
|
b1111111111111110 g#
|
bx g#
|
b0 f#
|
bx f#
|
bx e#
|
0e#
|
bx d#
|
bx d#
|
bx c#
|
b0 c#
|
bx b#
|
b0 b#
|
bx a#
|
0a#
|
bx `#
|
0`#
|
bx _#
|
b100 _#
|
b0xx00 ^#
|
b0 ^#
|
bx ]#
|
bx ]#
|
bx \#
|
bx \#
|
bx [#
|
bx [#
|
bx Z#
|
bx Z#
|
bx Y#
|
bx Y#
|
xX#
|
0X#
|
bx W#
|
xW#
|
bx V#
|
xV#
|
bx U#
|
xU#
|
bx T#
|
xT#
|
bx S#
|
xS#
|
bx R#
|
xR#
|
bx Q#
|
xQ#
|
bx P#
|
xP#
|
bx O#
|
xO#
|
bx N#
|
xN#
|
xM#
|
xM#
|
xL#
|
xL#
|
0K#
|
xK#
|
0J#
|
xJ#
|
bx I#
|
xI#
|
bx H#
|
bx H#
|
xG#
|
bx G#
|
xF#
|
xF#
|
bx E#
|
0E#
|
b0 D#
|
0D#
|
b0 C#
|
bx C#
|
xB#
|
bx B#
|
xA#
|
bx0 A#
|
0@#
|
b0xxxxxxx @#
|
0?#
|
bx ?#
|
0>#
|
bx >#
|
b0xx00 =#
|
bx0 =#
|
b0 <#
|
b0xxxxxxx <#
|
bx ;#
|
bx ;#
|
bx :#
|
bx :#
|
bx 9#
|
09#
|
bx 8#
|
08#
|
bx 7#
|
x7#
|
bx 6#
|
x6#
|
bx 5#
|
x5#
|
bx 4#
|
x4#
|
b1111111111111111 3#
|
x3#
|
b11111111 2#
|
x2#
|
01#
|
x1#
|
x0#
|
00#
|
x/#
|
x/#
|
x.#
|
0.#
|
x-#
|
x-#
|
x,#
|
x,#
|
x+#
|
b0xxxxxxx +#
|
x*#
|
bx0 *#
|
x)#
|
b0xxxxxxx )#
|
1(#
|
bx0 (#
|
1'#
|
bx '#
|
0&#
|
bx &#
|
0%#
|
bx %#
|
1$#
|
bx $#
|
x##
|
bx ##
|
1"#
|
bx "#
|
1!#
|
bx !#
|
1~"
|
x~"
|
1}"
|
0}"
|
x|"
|
b0xxxxxxxx |"
|
x{"
|
bx {"
|
xz"
|
bx z"
|
xy"
|
bx y"
|
1x"
|
b0xxxxxxxx x"
|
1w"
|
bx w"
|
1v"
|
bx v"
|
1u"
|
bx u"
|
xt"
|
bx t"
|
xs"
|
bx s"
|
xr"
|
1r"
|
xq"
|
0q"
|
b101 p"
|
bx p"
|
b101 o"
|
xo"
|
1n"
|
xn"
|
0m"
|
b0 m"
|
bx l"
|
b0 l"
|
0k"
|
0k"
|
b1 j"
|
0j"
|
b1 i"
|
b100 i"
|
bx h"
|
b0 h"
|
b1111111111111110 g"
|
bx g"
|
b11111110 f"
|
bx f"
|
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