URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb.v] - Diff between revs 2 and 4

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Rev 2	Rev 4
Line 2...	Line 2...
`* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com`	`* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com`
`*`	`*`
`* Distributed under the terms of the Lesser GPL`	`* Distributed under the terms of the Lesser GPL`
`*/`	`*/`
`timescale 1ns/1ns	`timescale 1ns/1ns
`include "MC6809_cpu.v"
`include "alu16.v"
`include "decoders.v"
`include "regblock.v"

`module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);`	`module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);`

`reg clk, reset;`	`reg clk, reset;`

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`always`	`always`
`#5 clk = ~clk;`	`#5 clk = ~clk;`

`MC6809_cpu cpu(`	`MC6809_cpu cpu(`
`.cpu_clk(clk),`	`.cpu_clk(clk),`
`.cpu_reset_n(reset),`	`.cpu_reset(reset),`
`.cpu_we_o(we),`	`.cpu_we_o(we),`
`.cpu_oe_o(oe),`	`.cpu_oe_o(oe),`
`.cpu_addr_o(addr),`	`.cpu_addr_o(addr),`
`.cpu_data_i(data_i),`	`.cpu_data_i(data_i),`
`.cpu_data_o(data_o)`	`.cpu_data_o(data_o)`
Line 35...	Line 31...

`initial`	`initial`
`begin`	`begin`
`$dumpvars;`	`$dumpvars;`
`clk = 0;`	`clk = 0;`
`reset = 0;`	`reset = 1;`
`#0`	`#0`
`#46`	`#46`
`reset = 1;`	`reset = 0;`
`#2000`	`#5000`
`$finish;`	`$finish;`
`end`	`end`

`endmodule`	`endmodule`

Line 76...	Line 72...

`always @(negedge oe)`	`always @(negedge oe)`
`begin`	`begin`
`$display("R %04x = %02x %t", addr, mem[addr], $time);`	`$display("R %04x = %02x %t", addr, mem[addr], $time);`
`end`	`end`
//`define READTESTBIN	`define READTESTBIN
`integer i;`	`integer i;`
`initial`	`initial`
`begin`	`begin`
`ifdef READTESTBIN	`ifdef READTESTBIN
`$readmemh("instructions_test.hex", mem);`	`$readmemh("instructions_test.hex", mem);`
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`mem[16'hfffe] = 8'h00; // setup reset`	`mem[16'hfffe] = 8'h00; // setup reset`
`mem[16'hffff] = 8'h00;`	`mem[16'hffff] = 8'h00;`
`else	`else
`for (i = 0; i < 65536; i=i+1)`	`for (i = 0; i < 65536; i=i+1)`
`mem[i] = 8'ha5;`	`mem[i] = 8'ha5;`
	`/*`
`mem[16'h1000] = 8'h3f; // lda #$10`	`mem[16'h1000] = 8'h3f; // lda #$10`
`mem[16'h1001] = 8'h10; //`	`mem[16'h1001] = 8'h10; //`
`mem[16'h1002] = 8'hc6; // ldb #$12`	`mem[16'h1002] = 8'hc6; // ldb #$12`
`mem[16'h1003] = 8'h12; //`	`mem[16'h1003] = 8'h12; //`

`mem[16'h1004] = 8'h3d; // mul`	`mem[16'h1004] = 8'h3d; // mul`
`mem[16'h1005] = 8'h4c; // inca`	`mem[16'h1005] = 8'h4c; // inca`
`mem[16'h1006] = 8'h5c; // incb`	`mem[16'h1006] = 8'h5c; // incb`

`mem[16'h1007] = 8'h9d; // jsr`	`mem[16'h1007] = 8'h9d; // jsr`
`mem[16'h1008] = 8'h0e; //`	`mem[16'h1008] = 8'h0e; //`
`mem[16'h1009] = 8'h12; // nop`	`mem[16'h1009] = 8'h12; // nop`

`mem[16'h100a] = 8'h20; // bre *`	`mem[16'h100a] = 8'h20; // bre *`
`mem[16'h100b] = 8'hfe; //`	`mem[16'h100b] = 8'hfe; //`
`mem[16'h100c] = 8'h12; //`	`mem[16'h100c] = 8'h12; //`
`mem[16'h100d] = 8'h39; //`	`mem[16'h100d] = 8'h39; //`
`mem[16'h100e] = 8'h39; //`	`mem[16'h100e] = 8'h39; //`

`mem[16'h2000] = 8'h3b; // rti`	`mem[16'h2000] = 8'h3b; // rti`
`mem[16'h2002] = 8'h3b; // rti`	`mem[16'h2002] = 8'h3b; // rti`
`mem[16'h2004] = 8'h3b; // rti`	`mem[16'h2004] = 8'h3b; // rti`
`mem[16'h2006] = 8'h3b; // rti`	`mem[16'h2006] = 8'h3b; // rti`
`mem[16'h2008] = 8'h3b; // rti`	`mem[16'h2008] = 8'h3b; // rti`
`mem[16'h200a] = 8'h3b; // rti`	`mem[16'h200a] = 8'h3b; // rti`
`mem[16'h200c] = 8'h3b; // rti`	`mem[16'h200c] = 8'h3b; // rti`
`mem[16'h200e] = 8'h3b; // rti`	`mem[16'h200e] = 8'h3b; // rti`
	`*/`

`/*`	`/*`
`// test indexed store`	`// test indexed store`
`mem[16'h1000] = 8'h86; // lda #$fe`	`mem[16'h1000] = 8'h86; // lda #$02`
`mem[16'h1001] = 8'h02; //`	`mem[16'h1001] = 8'h02; //`
`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`	`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
`mem[16'h1003] = 8'h00; //`	`mem[16'h1003] = 8'h00; //`

`mem[16'h1004] = 8'ha7; // lda ,x`	`mem[16'h1004] = 8'ha7; // lda ,x`
Line 185...	Line 181...
`mem[16'h1014] = 8'b10001001; //`	`mem[16'h1014] = 8'b10001001; //`
`mem[16'h1015] = 8'h00; //`	`mem[16'h1015] = 8'h00; //`
`mem[16'h1016] = 8'h00; //`	`mem[16'h1016] = 8'h00; //`
`*/`	`*/`

`/* test extended`	`/* test extended*/`
`mem[16'h1000] = 8'hc6; // ldb #$fe`	`mem[16'h1000] = 8'h86; // ldb #$fe`
`mem[16'h1001] = 8'hfe; //`	`mem[16'h1001] = 8'h02; //`
`mem[16'h1002] = 8'h86; // lda #$0`	`mem[16'h1002] = 8'hc6; // lda #$0`
`mem[16'h1003] = 8'h00; //`	`mem[16'h1003] = 8'h00; //`

`mem[16'h1004] = 8'h4c; // inca`	`mem[16'h1004] = 8'h97; // inca`
`mem[16'h1005] = 8'hb7; // sta $0000`	`mem[16'h1005] = 8'h00; // sta $0000`
`mem[16'h1006] = 8'h00; //`	`mem[16'h1006] = 8'hd7; //`
`mem[16'h1007] = 8'h00; //`	`mem[16'h1007] = 8'h01; //`


`mem[16'h1008] = 8'hb6; // lda $0000`	`mem[16'h1008] = 8'hb6; // lda $0000`
`mem[16'h1009] = 8'h00; //`	`mem[16'h1009] = 8'h00; //`
`mem[16'h100a] = 8'h00; //`	`mem[16'h100a] = 8'h00; //`

`mem[16'h100b] = 8'h26; // bne$.-5`	`mem[16'h100b] = 8'h26; // bne$.-5`
`mem[16'h100c] = 8'hf7; //`	`mem[16'h100c] = 8'hf7; //`

`mem[16'h100d] = 8'h5c; // incb`	`mem[16'h100d] = 8'h5c; // incb`

`mem[16'h100e] = 8'hf7; // stb $0001`	`mem[16'h100e] = 8'hf7; // stb $0001`
`mem[16'h100f] = 8'h00; //`	`mem[16'h100f] = 8'h00; //`
`mem[16'h1010] = 8'h01; //`	`mem[16'h1010] = 8'h01; //`

`mem[16'h1011] = 8'h20; // bra`	`mem[16'h1011] = 8'h20; // bra`
`mem[16'h1012] = 8'hec; // $.-18`	`mem[16'h1012] = 8'hec; // $.-18`
`*/`	`//*/`
`mem[16'hfff0] = 8'h20; // reset`	`mem[16'hfff0] = 8'h20; // reset`
`mem[16'hfff1] = 8'h00;`	`mem[16'hfff1] = 8'h00;`
`mem[16'hfff2] = 8'h20; // reset`	`mem[16'hfff2] = 8'h20; // reset`
`mem[16'hfff3] = 8'h02;`	`mem[16'hfff3] = 8'h02;`
`mem[16'hfff4] = 8'h20; // reset`	`mem[16'hfff4] = 8'h20; // reset`

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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb.v] - Diff between revs 2 and 4