| Line 10... |
Line 10... |
module CC3_top(
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module CC3_top(
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input wire clk40_i,
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input wire clk40_i,
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/* CPU Bus */
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/* CPU Bus */
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output wire cpuclk_o,
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output wire cpuclk_o,
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output wire reset_o,
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output wire reset_o,
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output wire [15:0] addr_o,
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output wire [18:0] addr_o,
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output wire oen_o,
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output wire oen_o,
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output wire wen_o,
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output wire wen_o,
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output wire cen_o,
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output wire cen_o,
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output wire [7:0] data_io,
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inout wire [15:0] data_io,
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output wire [5:0] state_o,
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output wire [5:0] state_o,
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/* Debug */
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/* Debug */
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output wire [7:0] leds_o,
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output wire [7:0] leds_o,
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/* VGA output */
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/* VGA output */
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output wire hsync_o,
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output wire hsync_o,
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output wire vsync_o,
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output wire vsync_o,
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output wire red_o,
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output wire red_o,
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output wire green_o,
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output wire green_o,
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output wire blue_o
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output wire blue_o,
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/* logic analyzer probe */
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output wire [5:0] laddr_o,
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output wire loen_o,
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output wire lwen_o,
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output wire lcen_o,
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output wire [7:0] ldata_io
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);
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);
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reg cpu_clk, clk_div2;
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reg cpu_clk, clk_div2;
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reg [3:0] reset_cnt;
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reg [3:0] reset_cnt;
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| Line 36... |
Line 42... |
/* CPU IO */
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/* CPU IO */
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wire [15:0] cpu0_addr_o, cpu1_addr_o;
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wire [15:0] cpu0_addr_o, cpu1_addr_o;
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wire [7:0] cpu0_data_in, cpu0_data_out, cpu1_data_in, cpu1_data_out;
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wire [7:0] cpu0_data_in, cpu0_data_out, cpu1_data_in, cpu1_data_out;
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wire cpu0_we, cpu0_oe, cpu1_we, cpu1_oe, cpu_reset;
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wire cpu0_we, cpu0_oe, cpu1_we, cpu1_oe, cpu_reset;
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wire [5:0] cpu0_state;
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wire [5:0] cpu0_state;
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/* Memory */
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wire bios_en, video_en, extram_en;
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wire [7:0] data_from_bios, data_from_video;
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assign bios_en = cpu0_addr_o[15:12] == 4'hf;
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assign video_en = cpu0_addr_o[15:12] == 4'he;
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assign extram_en = !(bios_en | video_en);
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assign cpu0_data_in = bios_en ? data_from_bios:
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video_en ? data_from_video:data_io[7:0];
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wire debug_data;
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/* Module io */
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/* Module io */
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assign addr_o = cpu0_addr_o;
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assign addr_o = { 3'b000, cpu0_addr_o };
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assign data_io = cpu0_we ? cpu0_data_out:cpu0_data_in;
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assign data_io = { 8'hzz, cpu0_we ? cpu0_data_out:8'hzz };
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/*
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assign hsync_o = 0;
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assign vsync_o = 0;
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assign red_o = 0;
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assign green_o = 0;
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assign blue_o = 0;
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*/
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assign leds_o = leds_r;
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assign leds_o = leds_r;
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assign oen_o = !cpu0_oe;
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assign oen_o = !cpu0_oe;
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assign wen_o = cpu0_we & (cpu0_addr_o[15:12] == 4'h0);
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assign wen_o = !cpu0_we;
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assign cen_o = !(cpu0_oe | cpu0_we);
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assign cen_o = !extram_en;// !(extram_en & (cpu0_oe | cpu0_we));
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assign cpuclk_o = cpu_clk;
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assign cpuclk_o = cpu_clk;
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assign reset_o = cpu_reset;
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assign reset_o = cpu_reset;
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assign state_o = cpu0_state;
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assign state_o = /*{ bios_en, video_en, extram_en };*/cpu0_state;
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/* logic analyzer probe */
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assign laddr_o = cpu0_addr_o[5:0]; //debug_data[15:9];
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assign ldata_io = data_io[7:0];//cpu0_we ? cpu0_data_out:cpu0_data_in;//debug_data[7:0];
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assign loen_o = !cpu0_oe;
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assign lwen_o = !cpu0_we;
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assign lcen_o = ! (extram_en & (cpu0_oe | cpu0_we));
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`ifdef SERIAL_DEBUG
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reg [7:0] div;
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always @(posedge clk40_i)
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always @(posedge clk40_i)
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cpu_clk <= !cpu_clk;
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begin
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if (!cpu_reset)
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begin
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if (div == 65)
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div <= 0;
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else
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div <= div + 1;
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end
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end
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always @(posedge clk40_i)
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if (div < 8'h2)
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cpu_clk <= 1'b1;
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else
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cpu_clk <= 1'b0;
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`else
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reg div;
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always @(posedge clk40_i)
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div <= ~div;
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always @(posedge div)
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cpu_clk <= ~cpu_clk;
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`endif
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assign cpu_reset = reset_cnt != 4'd14;
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assign cpu_reset = reset_cnt != 4'd14;
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always @(posedge cpu_clk)
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always @(posedge clk40_i)
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begin
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begin
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if (reset_cnt != 4'd14)
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if (reset_cnt != 4'd14)
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reset_cnt <= reset_cnt + 4'h1;
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reset_cnt <= reset_cnt + 4'h1;
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if (cpu0_we)
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if (cpu0_we)
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leds_r <= cpu0_data_out;
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leds_r <= cpu0_data_out[7:0];
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end
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end
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MC6809_cpu cpu0(
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MC6809_cpu cpu0(
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.cpu_clk(cpu_clk),
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.cpu_clk(cpu_clk),
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| Line 81... |
Line 127... |
.cpu_state_o(cpu0_state),
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.cpu_state_o(cpu0_state),
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.cpu_we_o(cpu0_we),
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.cpu_we_o(cpu0_we),
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.cpu_oe_o(cpu0_oe),
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.cpu_oe_o(cpu0_oe),
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.cpu_addr_o(cpu0_addr_o),
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.cpu_addr_o(cpu0_addr_o),
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.cpu_data_i(cpu0_data_in),
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.cpu_data_i(cpu0_data_in),
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.cpu_data_o(cpu0_data_out)
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.cpu_data_o(cpu0_data_out),
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.debug_clk(clk40_i),
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.debug_data_o(debug_data)
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);
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);
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/* Memory */
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/* Memory */
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wire bios_en, video_en;
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wire [7:0] data_from_bios, data_from_video;
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assign bios_en = cpu0_addr_o[15:12] == 4'hf;
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assign video_en = cpu0_addr_o[15:12] == 4'h0;
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assign cpu0_data_in = bios_en ? data_from_bios:
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video_en ? data_from_video:8'hzz;
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bios2k bios(
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bios2k bios(
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.DataInA(cpu0_data_out[7:0]),
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.DataInA(cpu0_data_out[7:0]),
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.DataInB(cpu1_data_out[7:0]),
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.DataInB(cpu1_data_out[7:0]),
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.AddressA(cpu0_addr_o[10:0]),
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.AddressA(cpu0_addr_o[10:0]),
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