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# Synospys Constraint Checker(syntax only), version maplat, Build 618R, built Mar 14 2013
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# Synospys Constraint Checker(syntax only), version maplat, Build 800R, built Nov 18 2013
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# Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
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# Written on Thu Feb 6 15:34:39 2014
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# Written on Sun Jul 06 07:46:29 2014
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##### DESIGN INFO #######################################################
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##### DESIGN INFO #######################################################
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Top View: "CC3_top"
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Top View: "CC3_top"
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Start Requested Requested Clock Clock
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Start Requested Requested Clock Clock
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Clock Frequency Period Type Group
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Clock Frequency Period Type Group
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CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
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CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
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CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
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CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
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CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
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CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
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====================================================================================================================
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====================================================================================================================
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