Subversion Repositories 6809_6309_compatible_core

Date:        Wed Jan  1 11:05:21 2014

Date:        Sun Jan  5 08:22:47 2014

Run Time:00h:00m:00s

Run Time:00h:00m:01s

Run Time:00h:00m:16s

Run Time:00h:00m:17s

#Wed Jan  1 11:05:21 2014

#Sun Jan  5 08:22:47 2014

@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":727:23:727:27|Specified digits overflow the number's size

@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":698:23:698:27|Specified digits overflow the number's size

Options changed - recompiling

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v changed - recompiling

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":445:6:445:13|Ignoring system task $display

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":417:6:417:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1017:0:1017:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1033:0:1033:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.

# Wed Jan  1 11:05:23 2014

# Sun Jan  5 08:22:49 2014

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 136MB)

# Wed Jan  1 11:05:25 2014

# Sun Jan  5 08:22:51 2014

Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 156MB)

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 157MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 156MB)

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 158MB)

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 162MB)

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 158MB)

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register ACCB[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register k_ind_ea[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register cff pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":253:2:253:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]

Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 162MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)

Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 162MB)

Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 158MB)

Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 189MB peak: 227MB)

Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 197MB peak: 226MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 164MB peak: 227MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 165MB peak: 226MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 227MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 226MB)

233 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

281 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 169MB peak: 227MB)

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 169MB peak: 226MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 227MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 226MB)

# Timing Report written on Wed Jan  1 11:05:41 2014

# Timing Report written on Sun Jan  5 08:23:08 2014

Worst slack in design: 978.215

Worst slack in design: 979.333

CC3_top|clk40_i     1.0 MHz       45.9 MHz      1000.000      21.785        978.215     inferred     Inferred_clkgroup_0

CC3_top|clk40_i     1.0 MHz       48.4 MHz      1000.000      20.667        979.333     inferred     Inferred_clkgroup_0

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.215  |  No paths    -      |  No paths    -      |  No paths    -

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    979.333  |  No paths    -      |  No paths    -      |  No paths    -

---------------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------

cpu0.k_opcode[2]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]               1.374       978.215

cpu0.regs.SU_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_ea_reg_sn_N_3f     1.268       979.333

cpu0.k_opcode[0]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]               1.361       978.228

cpu0.regs.SS_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SS_pipe_20             1.268       979.397

cpu0.k_opcode[1]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]               1.366       978.263

cpu0.regs.SU_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_19             1.044       979.557

cpu0.k_opcode[6]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]               1.336       978.293

cpu0.regs.SU_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_20             1.044       979.557

cpu0.k_opcode[7]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]               1.352       978.341

cpu0.k_opcode[1]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]            1.387       979.562

cpu0.regs.SU_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_4_sqmuxaf          1.268       978.356

cpu0.k_opcode[0]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]            1.358       979.591

cpu0.regs.SU_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       SU_1_sqmuxa_5f            1.268       978.356

cpu0.regs.SS_pipe_18     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[0]          1.044       979.621

cpu0.regs.SS_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       SS_1_sqmuxa_2f            1.268       978.420

cpu0.regs.SS_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[0]          1.044       979.621

cpu0.regs.SS_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_0_sqmuxa_1_snf     1.268       978.420

cpu0.regs.SS_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[1]          0.972       979.908

cpu0.k_opcode[3]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]               1.385       978.484

cpu0.regs.SS_pipe_22     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[1]          0.972       979.908

===============================================================================================================

===========================================================================================================

cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      978.215

cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      979.333

cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      978.215

cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      979.333

cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      978.358

cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      979.476

cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      978.358

cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      979.476

cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      978.501

cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      979.619

cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      978.501

cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      979.619

cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      978.644

cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      979.794

cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      978.644

cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      979.794

cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      978.786

cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      979.937

cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      978.786

cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      979.937

    - Propagation time:                      21.679

    - Propagation time:                      20.561

    = Slack (critical) :                     978.215

    = Slack (critical) :                     979.333

    Number of logic level(s):                22

    Number of logic level(s):                21

    Starting point:                          cpu0.k_opcode[2] / Q

    Starting point:                          cpu0.regs.SU_pipe_21 / Q

------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------

cpu0.k_opcode[2]                                          FD1P3AX      Q        Out     1.374     1.374       -

cpu0.regs.SU_pipe_21                     FD1P3AX      Q        Out     1.268     1.268       -

k_opcode[2]                                               Net          -        -       -         -           63

un1_ea_reg_sn_N_3f                       Net          -        -       -         -           17

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     B        In      0.000     1.374       -

cpu0.regs.un1_ea_reg[0]                  ORCALUT4     C        In      0.000     1.268       -

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     Z        Out     1.193     2.567       -

cpu0.regs.un1_ea_reg[0]                  ORCALUT4     Z        Out     1.153     2.421       -

state_3_sqmuxa_1                                          Net          -        -       -         -           4

N_289                                    Net          -        -       -         -           3

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     C        In      0.000     2.567       -

cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        B1       In      0.000     2.421       -

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     Z        Out     1.193     3.760       -

cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        COUT     Out     1.544     3.965       -

dest_reg_5_sqmuxa                                         Net          -        -       -         -           4

un1_ea_reg_2_cry_0                       Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     B        In      0.000     3.760       -

cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        CIN      In      0.000     3.965       -

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     Z        Out     1.017     4.777       -

cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        S1       Out     1.765     5.730       -

un1_dest_reg44_1_1                                        Net          -        -       -         -           1

SU[2]                                    Net          -        -       -         -           6

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     D        In      0.000     4.777       -

cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     C        In      0.000     5.730       -

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     Z        Out     1.017     5.793       -

cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     Z        Out     1.017     6.747       -

un1_dest_reg44_1_2                                        Net          -        -       -         -           1

ea_reg_3_am[2]                           Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     A        In      0.000     5.793       -

cpu0.regs.ea_reg_3[2]                    PFUMX        BLUT     In      0.000     6.747       -

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     Z        Out     1.153     6.946       -

cpu0.regs.ea_reg_3[2]                    PFUMX        Z        Out     0.390     7.137       -

un1_dest_reg44_1                                          Net          -        -       -         -           3

ea_reg[2]                                Net          -        -       -         -           4

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     B        In      0.000     6.946       -

cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     A        In      0.000     7.137       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     Z        Out     1.089     8.035       -

cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     Z        Out     1.017     8.154       -

path_left_addr_2_sqmuxa                                   Net          -        -       -         -           2

N_506                                    Net          -        -       -         -           1

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     A        In      0.000     8.035       -

cpu0.regs.eamem_addr_cry_1_0             CCU2D        C1       In      0.000     8.154       -

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     Z        Out     1.225     9.260       -

cpu0.regs.eamem_addr_cry_1_0             CCU2D        COUT     Out     1.544     9.698       -

path_left_addr_1_sqmuxa_2                                 Net          -        -       -         -           5

eamem_addr_cry_2                         Net          -        -       -         -           1

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     A        In      0.000     9.260       -

cpu0.regs.eamem_addr_cry_3_0             CCU2D        CIN      In      0.000     9.698       -

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     Z        Out     1.193     10.453      -

cpu0.regs.eamem_addr_cry_3_0             CCU2D        COUT     Out     0.143     9.841       -

path_left_addr_sn_N_2                                     Net          -        -       -         -           4

eamem_addr_cry_4                         Net          -        -       -         -           1

cpu0.dec_regs.path_left_addr[3]                           PFUMX        C0       In      0.000     10.453      -

cpu0.regs.eamem_addr_cry_5_0             CCU2D        CIN      In      0.000     9.841       -

cpu0.dec_regs.path_left_addr[3]                           PFUMX        Z        Out     1.089     11.542      -

cpu0.regs.eamem_addr_cry_5_0             CCU2D        COUT     Out     0.143     9.984       -

dec_o_left_path_addr[3]                                   Net          -        -       -         -           4

eamem_addr_cry_6                         Net          -        -       -         -           1

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     A        In      0.000     11.542      -

cpu0.regs.eamem_addr_cry_7_0             CCU2D        CIN      In      0.000     9.984       -

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     Z        Out     1.369     12.910      -

cpu0.regs.eamem_addr_cry_7_0             CCU2D        COUT     Out     0.143     10.127      -

datamux_o_alu_in_left_path_addr[3]                        Net          -        -       -         -           34

eamem_addr_cry_8                         Net          -        -       -         -           1

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     D        In      0.000     12.910      -

cpu0.regs.eamem_addr_cry_9_0             CCU2D        CIN      In      0.000     10.127      -

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     Z        Out     1.313     14.223      -

cpu0.regs.eamem_addr_cry_9_0             CCU2D        S0       Out     1.685     11.812      -

N_784                                                     Net          -        -       -         -           16

regs_o_eamem_addr[9]                     Net          -        -       -         -           3

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     C        In      0.000     14.223      -

cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     A        In      0.000     11.812      -

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     Z        Out     1.017     15.240      -

cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     Z        Out     1.089     12.901      -

path_left_data_bm[3]                                      Net          -        -       -         -           1

datamux_o_dest_6[9]                      Net          -        -       -         -           2

cpu0.regs.path_left_data[3]                               PFUMX        ALUT     In      0.000     15.240      -

cpu0.regs.k_new_pc_1[9]                  ORCALUT4     A        In      0.000     12.901      -

cpu0.regs.path_left_data[3]                               PFUMX        Z        Out     0.350     15.590      -

cpu0.regs.k_new_pc_1[9]                  ORCALUT4     Z        Out     1.017     13.917      -

regs_o_left_path_data[3]                                  Net          -        -       -         -           3

N_953                                    Net          -        -       -         -           1

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     A        In      0.000     15.590      -

cpu0.regs.k_new_pc_2[9]                  ORCALUT4     A        In      0.000     13.917      -

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     Z        Out     1.265     16.855      -

cpu0.regs.k_new_pc_2[9]                  ORCALUT4     Z        Out     1.017     14.934      -

left_1[3]                                                 Net          -        -       -         -           8

N_969                                    Net          -        -       -         -           1

cpu0.regs.PC_11[3]                                        ORCALUT4     C        In      0.000     16.855      -

cpu0.regs.k_new_pc_5[9]                  ORCALUT4     A        In      0.000     14.934      -

cpu0.regs.PC_11[3]                                        ORCALUT4     Z        Out     1.017     17.872      -

cpu0.regs.k_new_pc_5[9]                  ORCALUT4     Z        Out     1.017     15.951      -

PC_11[3]                                                  Net          -        -       -         -           1

k_new_pc[9]                              Net          -        -       -         -           1

cpu0.regs.PC_cry_0[2]                                     CCU2D        B1       In      0.000     17.872      -

cpu0.regs.PC_11_am[9]                    ORCALUT4     A        In      0.000     15.951      -

cpu0.regs.PC_cry_0[2]                                     CCU2D        COUT     Out     1.544     19.416      -

cpu0.regs.PC_11_am[9]                    ORCALUT4     Z        Out     1.017     16.968      -

PC_cry[3]                                                 Net          -        -       -         -           1

PC_11_am[9]                              Net          -        -       -         -           1

cpu0.regs.PC_cry_0[4]                                     CCU2D        CIN      In      0.000     19.416      -

cpu0.regs.PC_11[9]                       PFUMX        BLUT     In      0.000     16.968      -

cpu0.regs.PC_cry_0[4]                                     CCU2D        COUT     Out     0.143     19.559      -

cpu0.regs.PC_11[9]                       PFUMX        Z        Out     0.214     17.182      -

PC_cry[5]                                                 Net          -        -       -         -           1

PC_11[9]                                 Net          -        -       -         -           1

cpu0.regs.PC_cry_0[6]                                     CCU2D        CIN      In      0.000     19.559      -

cpu0.regs.PC_cry_0[8]                    CCU2D        B1       In      0.000     17.182      -

cpu0.regs.PC_cry_0[6]                                     CCU2D        COUT     Out     0.143     19.702      -

cpu0.regs.PC_cry_0[8]                    CCU2D        COUT     Out     1.544     18.727      -

cpu0.regs.PC_cry_0[10]                                    CCU2D        CIN      In      0.000     19.845      -

cpu0.regs.PC_cry_0[10]                   CCU2D        CIN      In      0.000     18.727      -

cpu0.regs.PC_cry_0[10]                                    CCU2D        COUT     Out     0.143     19.988      -

cpu0.regs.PC_cry_0[10]                   CCU2D        COUT     Out     0.143     18.869      -

cpu0.regs.PC_cry_0[12]                                    CCU2D        CIN      In      0.000     19.988      -

cpu0.regs.PC_cry_0[12]                   CCU2D        CIN      In      0.000     18.869      -

cpu0.regs.PC_cry_0[12]                                    CCU2D        COUT     Out     0.143     20.130      -

cpu0.regs.PC_cry_0[12]                   CCU2D        COUT     Out     0.143     19.012      -

cpu0.regs.PC_cry_0[14]                                    CCU2D        CIN      In      0.000     20.130      -

cpu0.regs.PC_cry_0[14]                   CCU2D        CIN      In      0.000     19.012      -

cpu0.regs.PC_cry_0[14]                                    CCU2D        S1       Out     1.549     21.679      -

cpu0.regs.PC_cry_0[14]                   CCU2D        S1       Out     1.549     20.561      -

cpu0.regs.PC[15]                                          FD1P3AX      D        In      0.000     21.679      -

cpu0.regs.PC[15]                         FD1P3AX      D        In      0.000     20.561      -

========================================================================================================================

=======================================================================================================

Register bits: 500 of 6864 (7%)

Register bits: 488 of 6864 (7%)

Block Rams : 2 of 26 (7%)

Block Rams : 10 of 26 (38%)

CCU2D:          160

CCU2D:          196

DP8KC:          2

DP8KC:          10

FD1P3AX:        484

FD1P3AX:        441

FD1S3AX:        1

FD1S3AX:        28

INV:            13

INV:            20

L6MUX21:        31

L6MUX21:        37

OB:             48

OB:             40

OFS1P3DX:       8

OBZ:            8

ORCALUT4:       1933

OFS1P3DX:       9

PFUMX:          308

OFS1P3IX:       1

VHI:            8

VHI:            10

VLO:            13

VLO:            16

true:           5

true:           6

At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 44MB peak: 227MB)

At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 43MB peak: 226MB)

Process took 0h:00m:15s realtime, 0h:00m:15s cputime

Process took 0h:00m:16s realtime, 0h:00m:16s cputime

# Wed Jan  1 11:05:41 2014

# Sun Jan  5 08:23:08 2014

  On or above line 280 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 310 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 288 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 318 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1928 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 9904 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 5198 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10621 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 9990 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10919 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10297 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 11654 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 11284 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 12094 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 11361 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 13053 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 12803 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15901 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15684 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 28685 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 29797 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 31454 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32207 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 34211 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32625 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 34629 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38016 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 40141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38686 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 40954 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - ngdbuild: DRC complete with 96 warnings

WARNING - ngdbuild: DRC complete with 117 warnings

   3018 blocks expanded

   3125 blocks expanded

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_3_i' to infer global GSR net.

WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.

   Number of registers:    500

   Number of registers:    488

      PFU registers:    492

      PFU registers:    478

      PIO registers:    8

      PIO registers:    10

   Number of SLICEs:          1135 out of  3432 (33%)

   Number of SLICEs:          1219 out of  3432 (36%)

      SLICEs(logic/ROM/RAM):   277 out of  2574 (11%)

      SLICEs(logic/ROM/RAM):   361 out of  2574 (14%)

          As Logic/ROM:    277 out of  2574 (11%)

          As Logic/ROM:    361 out of  2574 (14%)

   Number of logic LUT4s:     1946

   Number of logic LUT4s:     2044

   Number of ripple logic:    160 (320 LUT4s)

   Number of ripple logic:    196 (392 LUT4s)

   Total number of LUT4s:     2266

   Total number of LUT4s:     2436

   Number of block RAMs:  2 out of 26 (8%)

   Number of block RAMs:  10 out of 26 (38%)

     Net cpu_clkgen: 312 loads, 312 rising, 0 falling (Driver: PIO clk40_i )

     Net cpu_clkgen: 305 loads, 305 rising, 0 falling (Driver: PIO clk40_i )

   Number of Clock Enables:  27

   Number of Clock Enables:  35

     Net cpu_clk: 127 loads, 127 LSLICEs

     Net cpu_clk: 97 loads, 97 LSLICEs

     Net un1_cen_o_0: 4 loads, 0 LSLICEs

     Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs

     Net cpu0/state_9_sqmuxa_RNILUGF3: 3 loads, 3 LSLICEs

     Net textctrl/line_cnte: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_21_RNI2O3K: 4 loads, 4 LSLICEs

     Net textctrl/y_cnte: 4 loads, 4 LSLICEs

     Net cpu0/mode52_3_RNIE4HVB: 4 loads, 4 LSLICEs

     Net textctrl/x_cnte: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_77_RNIJP1NM: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_12_1_RNIGGP7P: 4 loads, 4 LSLICEs

     Net cpu0/un1_k_opcode_3_RNIGMC4I: 8 loads, 8 LSLICEs

     Net cpu0/un1_cpu_reset_6_0_a3_1_RNI3DL77: 3 loads, 3 LSLICEs

     Net cpu0/k_new_pc27_0_RNI0JKSH: 4 loads, 4 LSLICEs

     Net cpu0/next_state10_RNIVT0PU: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_66_RNIVV3L4: 2 loads, 2 LSLICEs

     Net cpu0/un1_dest_reg44_1_0_a2_1_0_RNIUSPTD1: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_92_i_o4_RNIGQ812: 4 loads, 4 LSLICEs

     Net cpu0/un1_cpu_reset_5_0_a3_2_RNIUKBUL: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_18_2_RNITPBJ: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_18_2_RNI7CC51: 4 loads, 4 LSLICEs

     Net cpu0/k_cpu_we_3_RNIIAUK: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_56_RNI0KNU2: 8 loads, 8 LSLICEs

     Net cpu0/cff_0_sqmuxa_1_RNIICN5: 18 loads, 18 LSLICEs

     Net cpu0/regs/cff_0_sqmuxa_1_0_RNI212L: 7 loads, 7 LSLICEs

     Net cpu0/regs/IY_1_sqmuxa_1_1_RNIHDTU1: 25 loads, 25 LSLICEs

     Net cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1: 17 loads, 17 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_1_RNISEKK1: 25 loads, 25 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1: 19 loads, 19 LSLICEs

     Net cpu0/regs/DP_1_sqmuxa_0_0_RNIBPP91: 9 loads, 9 LSLICEs

     Net cpu0/regs/DP_1_sqmuxa_0_RNI70L71: 5 loads, 5 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 9 loads, 9 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 4 loads, 4 LSLICEs

     Net cpu0/regs/un1_exg_dest_r_4_RNIA9G72: 4 loads, 4 LSLICEs

     Net cpu0/regs/ACCB45_RNIMT5N2: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_74_1_RNIUBKOG: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_18_2_RNI3MPQ: 4 loads, 4 LSLICEs

     Net cpu0/state81_RNID4BE4: 2 loads, 2 LSLICEs

     Net cpu0/k_ofshi_cnv[0]: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIGK359: 4 loads, 4 LSLICEs

     Net cpu0/state_RNIGVAO2[5]: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNI57TP9: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_84_1_RNITNQJ9: 4 loads, 4 LSLICEs

     Net cpu0/k_memlo_1_sqmuxa_RNI6AUQ: 4 loads, 4 LSLICEs

   Number of local set/reset loads for net reset_o_c merged into GSR:  6

     Net cpu0/k_memhi_0_sqmuxa_RNI0T301: 4 loads, 4 LSLICEs

   Number of LSRs:  2

   Number of local set/reset loads for net cpu0.cpu_reset_i_3_i merged into GSR:  6

     Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs

   Number of LSRs:  1

     Net cpu0/G_7: 1 loads, 1 LSLICEs

     Net cpu_clk: 149 loads

     Net cpu_clk: 117 loads

     Net cpu0/dec_o_alu_opcode[0]: 95 loads

     Net state_o_c[1]: 103 loads

     Net state_o_c[1]: 95 loads

     Net cpu0/dec_o_alu_opcode[0]: 92 loads

     Net state_o_c[4]: 77 loads

     Net state_o_c[4]: 81 loads

     Net state_o_c[2]: 73 loads

     Net state_o_c[2]: 74 loads

     Net cpu0/k_opcode[3]: 70 loads

     Net cpu0/k_opcode[1]: 72 loads

     Net cpu0/dec_o_p1_mode[2]: 67 loads

     Net cpu0/dec_o_p1_mode[0]: 70 loads

     Net cpu0/dec_o_p1_mode[0]: 66 loads

     Net cpu0/dec_o_alu_opcode[3]: 63 loads

   Number of warnings:  3

   Number of warnings:  11

Peak Memory Usage: 193 MB

Peak Memory Usage: 195 MB

Wed Jan  1 11:05:44 2014

Sun Jan  5 08:23:12 2014

Timing errors: 4096  Score: 10215342

Timing errors: 1702  Score: 686102

Cumulative negative slack: 10215342

Cumulative negative slack: 686102

Constraints cover 3952043 paths, 1 nets, and 8655 connections (95.9% coverage)

Constraints cover 3270002 paths, 1 nets, and 9158 connections (96.1% coverage)

Wed Jan  1 11:05:44 2014

Sun Jan  5 08:23:12 2014

Constraints cover 3952043 paths, 1 nets, and 8953 connections (99.2% coverage)

Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)

Timing errors: 4096 (setup), 0 (hold)

Timing errors: 1702 (setup), 0 (hold)

Score: 10215342 (setup), 0 (hold)

Score: 686102 (setup), 0 (hold)

Cumulative negative slack: 10215342 (10215342+0)

Cumulative negative slack: 686102 (686102+0)

Wed Jan  1 11:05:44 2014

Sun Jan  5 08:23:12 2014

   IOLOGIC            8/336           2% used

   IOLOGIC           10/336           2% used

   SLICE           1135/3432         33% used

   SLICE           1219/3432         35% used

   EBR                2/26            7% used

   EBR               10/26           38% used

Number of Signals: 2562

Number of Signals: 2800

Number of Connections: 9028

Number of Connections: 9525

    cpu_clkgen (driver: clk40_i, clk load #: 312)

    cpu_clkgen (driver: clk40_i, clk load #: 305)

The following 5 signals are selected to use the secondary clock routing resources:

The following 4 signals are selected to use the secondary clock routing resources:

    cpu_clk (driver: SLICE_441, clk load #: 0, sr load #: 0, ce load #: 127)

    cpu_clk (driver: SLICE_407, clk load #: 0, sr load #: 0, ce load #: 97)

    cpu0/regs/IY_1_sqmuxa_1_1_RNIHDTU1 (driver: cpu0/regs/SLICE_927, clk load #: 0, sr load #: 0, ce load #: 25)

    cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1 (driver: cpu0/SLICE_803, clk load #: 0, sr load #: 0, ce load #: 19)

    cpu0/regs/IX_0_sqmuxa_1_1_RNISEKK1 (driver: cpu0/regs/SLICE_889, clk load #: 0, sr load #: 0, ce load #: 25)

    cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1 (driver: cpu0/SLICE_804, clk load #: 0, sr load #: 0, ce load #: 17)

    cpu0/cff_0_sqmuxa_1_RNIICN5 (driver: cpu0/regs/SLICE_1130, clk load #: 0, sr load #: 0, ce load #: 18)

    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_793, clk load #: 0, sr load #: 0, ce load #: 16)

Signal cpu0.cpu_reset_i_3_i is selected as Global Set/Reset.

Signal reset_o_c is selected as Global Set/Reset.

Placer score = 827523.

Placer score = 869535.

Finished Placer Phase 1.  REAL time: 12 secs

Finished Placer Phase 1.  REAL time: 13 secs

Placer score =  814815

Placer score =  857738

Finished Placer Phase 2.  REAL time: 13 secs

Finished Placer Phase 2.  REAL time: 14 secs

  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 312

  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 305

  SECONDARY "cpu_clk" from Q0 on comp "SLICE_441" on site "R21C18B", clk load = 0, ce load = 127, sr load = 0

  SECONDARY "cpu_clk" from Q0 on comp "SLICE_407" on site "R21C20C", clk load = 0, ce load = 97, sr load = 0

  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_803" on site "R21C18D", clk load = 0, ce load = 16, sr load = 0

  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_793" on site "R25C35A", clk load = 0, ce load = 16, sr load = 0

  SECONDARY "cpu0/cff_0_sqmuxa_1_RNIICN5" from F1 on comp "cpu0/regs/SLICE_1130" on site "R14C20C", clk load = 0, ce load = 18, sr load = 0

  SECONDARY "cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1" from F1 on comp "cpu0/SLICE_804" on site "R14C20A", clk load = 0, ce load = 17, sr load = 0

  SECONDARY "cpu0/regs/IY_1_sqmuxa_1_1_RNIHDTU1" from F0 on comp "cpu0/regs/SLICE_927" on site "R14C18A", clk load = 0, ce load = 25, sr load = 0

  SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1" from F1 on comp "cpu0/SLICE_803" on site "R14C18D", clk load = 0, ce load = 19, sr load = 0

  SECONDARY: 5 out of 8 (62%)

  SECONDARY: 4 out of 8 (50%)

Total placer CPU time: 12 secs

Total placer CPU time: 13 secs

0 connections routed; 9028 unrouted.

0 connections routed; 9525 unrouted.

Completed router resource preassignment. Real time: 16 secs

Completed router resource preassignment. Real time: 17 secs

Start NBR router at Wed Jan 01 11:06:00 CET 2014

Start NBR router at Sun Jan 05 08:23:29 CET 2014

Start NBR special constraint process at Wed Jan 01 11:06:00 CET 2014

Start NBR special constraint process at Sun Jan 05 08:23:29 CET 2014