| Line 16... |
Line 16... |
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,8-10,15) (VERI-1018) compiling module CC3_top
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,8-10,15) (VERI-1018) compiling module CC3_top
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,1-175,10) (VERI-9000) elaborating module 'CC3_top'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,1-175,10) (VERI-9000) elaborating module 'CC3_top'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(10,1-1115,10) (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(10,1-1137,10) (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v(8,1-171,10) (VERI-9000) elaborating module 'bios2k_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v(8,1-171,10) (VERI-9000) elaborating module 'bios2k_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v(2,1-192,10) (VERI-9000) elaborating module 'vgatext_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v(2,1-192,10) (VERI-9000) elaborating module 'vgatext_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(15,1-57,10) (VERI-9000) elaborating module 'alu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(15,1-61,10) (VERI-9000) elaborating module 'alu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(7,1-188,10) (VERI-9000) elaborating module 'regblock_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(7,1-188,10) (VERI-9000) elaborating module 'regblock_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(9,1-144,10) (VERI-9000) elaborating module 'decode_regs_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(9,1-152,10) (VERI-9000) elaborating module 'decode_regs_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(147,1-270,10) (VERI-9000) elaborating module 'decode_op_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(155,1-281,10) (VERI-9000) elaborating module 'decode_op_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(275,1-299,10) (VERI-9000) elaborating module 'decode_ea_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(286,1-310,10) (VERI-9000) elaborating module 'decode_ea_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(301,1-372,10) (VERI-9000) elaborating module 'decode_alu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(312,1-383,10) (VERI-9000) elaborating module 'decode_alu_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(374,1-410,10) (VERI-9000) elaborating module 'test_condition_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(385,1-422,10) (VERI-9000) elaborating module 'test_condition_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v(8,1-295,10) (VERI-9000) elaborating module 'fontrom_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v(8,1-295,10) (VERI-9000) elaborating module 'fontrom_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v(8,1-305,10) (VERI-9000) elaborating module 'textmem4k_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v(8,1-305,10) (VERI-9000) elaborating module 'textmem4k_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(198,1-323,10) (VERI-9000) elaborating module 'alu8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(604,1-628,10) (VERI-9000) elaborating module 'mul8x8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(326,1-602,10) (VERI-9000) elaborating module 'alu16_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(202,1-326,10) (VERI-9000) elaborating module 'alu8_uniq_1'
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(329,1-602,10) (VERI-9000) elaborating module 'alu16_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(191,1-285,10) (VERI-9000) elaborating module 'calc_ea_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(191,1-285,10) (VERI-9000) elaborating module 'calc_ea_uniq_1'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
|
| Line 47... |
Line 48... |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_8'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_8'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_9'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_9'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_10'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_10'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3'
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(62,1-79,10) (VERI-9000) elaborating module 'logic8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(66,1-83,10) (VERI-9000) elaborating module 'logic8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(85,1-123,10) (VERI-9000) elaborating module 'arith8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(89,1-127,10) (VERI-9000) elaborating module 'arith8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(158,1-195,10) (VERI-9000) elaborating module 'shift8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(162,1-199,10) (VERI-9000) elaborating module 'shift8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(604,1-628,10) (VERI-9000) elaborating module 'mul8x8_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(133,1-160,10) (VERI-9000) elaborating module 'arith16_uniq_1'
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(129,1-156,10) (VERI-9000) elaborating module 'arith16_uniq_1'
|
|
Done: design load finished with (0) errors, and (0) warnings
|
Done: design load finished with (0) errors, and (0) warnings
|
|
|
</PRE></BODY></HTML>
|
</PRE></BODY></HTML>
|
No newline at end of file
|
No newline at end of file
|
