URL
https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_acc.v] - Diff between revs 4 and 5
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 4 |
Rev 5 |
| Line 87... |
Line 87... |
begin
|
begin
|
if (rst)
|
if (rst)
|
data_out <= #1 `OC8051_RST_ACC;
|
data_out <= #1 `OC8051_RST_ACC;
|
else if (wad2)
|
else if (wad2)
|
data_out <= #1 data2_in;
|
data_out <= #1 data2_in;
|
else
|
else if (wr) begin
|
case ({wr, wr_bit})
|
if (!wr_bit) begin
|
2'b10: begin
|
|
if (wr_addr==`OC8051_SFR_ACC)
|
if (wr_addr==`OC8051_SFR_ACC)
|
data_out <= #1 data_in;
|
data_out <= #1 data_in;
|
end
|
end else begin
|
2'b11: begin
|
|
if (wr_addr[7:3]==`OC8051_SFR_B_ACC)
|
if (wr_addr[7:3]==`OC8051_SFR_B_ACC)
|
data_out[wr_addr[2:0]] <= #1 bit_in;
|
data_out[wr_addr[2:0]] <= #1 bit_in;
|
end
|
end
|
endcase
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) bit_out <= #1 1'b0;
|
if (rst) bit_out <= #1 1'b0;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
