URL
https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 82 and 123
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 82 |
Rev 123 |
| Line 44... |
Line 44... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.10 2003/01/13 14:14:40 simont
|
|
// replace some modules
|
|
//
|
// Revision 1.9 2002/09/30 17:33:59 simont
|
// Revision 1.9 2002/09/30 17:33:59 simont
|
// prepared header
|
// prepared header
|
//
|
//
|
//
|
//
|
|
|
| Line 309... |
Line 312... |
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation pcs Add
|
//operation pcs Add
|
`OC8051_ALU_PCS: begin
|
`OC8051_ALU_PCS: begin
|
if (src1[7]) begin
|
if (src1[7]) begin
|
des1 = src2+src1;
|
{desCy, des1} = {1'b0, src2} + {1'b0, src1};
|
des2 = src3;
|
des2 = {1'b0, src3} - {8'h0, !desCy};
|
end else {des2, des1} = {src3,src2} + {8'h00, src1};
|
end else {des2, des1} = {src3,src2} + {8'h00, src1};
|
desCy = 1'b0;
|
desCy = 1'b0;
|
desAc = 1'b0;
|
desAc = 1'b0;
|
desOv = 1'b0;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
| Line 340... |
Line 343... |
default: begin
|
default: begin
|
des1 = src1;
|
des1 = src1;
|
des2 = src2;
|
des2 = src2;
|
desCy = srcCy;
|
desCy = srcCy;
|
desAc = srcAc;
|
desAc = srcAc;
|
desOv = 1'bx;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.