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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Diff between revs 141 and 151

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Rev 141	Rev 151
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2003/05/06 09:41:35 simont`
	`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
	`//`
`// Revision 1.1 2003/01/13 14:13:12 simont`	`// Revision 1.1 2003/01/13 14:13:12 simont`
`// initial import`	`// initial import`
`//`	`//`
`//`	`//`
`//`	`//`
Line 78...	Line 81...
`output [7:0] src1, src2, src3;`	`output [7:0] src1, src2, src3;`

`reg [7:0] src1, src2, src3;`	`reg [7:0] src1, src2, src3;`

`reg [7:0] op1_r, op2_r, op3_r;`	`reg [7:0] op1_r, op2_r, op3_r;`
`reg [15:0] pc_r;`

`///////`	`///////`
`//`	`//`
`// src1`	`// src1`
`//`	`//`
`///////`	`///////`
`always @(sel1 or op1_r or op2_r or op3_r or pc_r or acc or ram)`	`always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)`
`begin`	`begin`
`case (sel1)`	`case (sel1)`
`OC8051_AS1_RAM: src1 = ram;	`OC8051_AS1_RAM: src1 = ram;
`OC8051_AS1_ACC: src1 = acc;	`OC8051_AS1_ACC: src1 = acc;
`OC8051_AS1_OP1: src1 = op1_r;	`OC8051_AS1_OP1: src1 = op1_r;
`OC8051_AS1_OP2: src1 = op2_r;	`OC8051_AS1_OP2: src1 = op2_r;
`OC8051_AS1_OP3: src1 = op3_r;	`OC8051_AS1_OP3: src1 = op3_r;
`OC8051_AS1_PCH: src1 = pc_r[15:8];	`OC8051_AS1_PCH: src1 = pc[15:8];
`OC8051_AS1_PCL: src1 = pc_r[7:0];	`OC8051_AS1_PCL: src1 = pc[7:0];
`default: src1 = 8'h00;`	`default: src1 = 8'h00;`
`endcase`	`endcase`
`end`	`end`

`///////`	`///////`
`//`	`//`
`// src2`	`// src2`
`//`	`//`
`///////`	`///////`
`always @(sel2 or op2_r or acc or ram or op1_r or pc)`	`always @(sel2 or op2_r or acc or ram or op1_r)`
`begin`	`begin`
`case (sel2)`	`case (sel2)`
`OC8051_AS2_ACC: src2= acc;	`OC8051_AS2_ACC: src2= acc;
`OC8051_AS2_ZERO: src2= 8'h00;	`OC8051_AS2_ZERO: src2= 8'h00;
`OC8051_AS2_RAM: src2= ram;	`OC8051_AS2_RAM: src2= ram;
Line 142...	Line 144...
`op1_r <= #1 op1;`	`op1_r <= #1 op1;`
`op2_r <= #1 op2;`	`op2_r <= #1 op2;`
`op3_r <= #1 op3;`	`op3_r <= #1 op3;`
`end`	`end`

`always @(posedge clk or posedge rst)`
`if (rst) begin`
`pc_r <= #1 16'h0;`
`end else if (rd) begin`
`pc_r <= #1 pc;`
`end`
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Diff between revs 141 and 151