| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/06/03 17:13:57 simont
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// remove pc_r register.
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//
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// Revision 1.2 2003/05/06 09:41:35 simont
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// Revision 1.2 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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//
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//
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// Revision 1.1 2003/01/13 14:13:12 simont
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// Revision 1.1 2003/01/13 14:13:12 simont
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// initial import
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// initial import
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| Line 89... |
Line 92... |
// src1
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// src1
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//
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//
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///////
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///////
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always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
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always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
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begin
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begin
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case (sel1)
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case (sel1) /* synopsys full_case parallel_case */
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`OC8051_AS1_RAM: src1 = ram;
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`OC8051_AS1_RAM: src1 = ram;
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`OC8051_AS1_ACC: src1 = acc;
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`OC8051_AS1_ACC: src1 = acc;
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`OC8051_AS1_OP1: src1 = op1_r;
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`OC8051_AS1_OP1: src1 = op1_r;
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`OC8051_AS1_OP2: src1 = op2_r;
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`OC8051_AS1_OP2: src1 = op2_r;
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`OC8051_AS1_OP3: src1 = op3_r;
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`OC8051_AS1_OP3: src1 = op3_r;
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`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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default: src1 = 8'h00;
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// default: src1 = 8'h00;
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endcase
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endcase
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end
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end
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///////
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///////
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//
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//
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// src2
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// src2
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//
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//
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///////
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///////
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always @(sel2 or op2_r or acc or ram or op1_r)
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always @(sel2 or op2_r or acc or ram or op1_r)
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begin
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begin
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case (sel2)
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case (sel2) /* synopsys full_case parallel_case */
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`OC8051_AS2_ACC: src2= acc;
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`OC8051_AS2_ACC: src2= acc;
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`OC8051_AS2_ZERO: src2= 8'h00;
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`OC8051_AS2_ZERO: src2= 8'h00;
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`OC8051_AS2_RAM: src2= ram;
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`OC8051_AS2_RAM: src2= ram;
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`OC8051_AS2_OP2: src2= op2_r;
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`OC8051_AS2_OP2: src2= op2_r;
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default: src2= 8'h00;
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// default: src2= 8'h00;
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endcase
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endcase
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end
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end
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///////
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///////
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//
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//
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| Line 125... |
Line 128... |
//
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//
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///////
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///////
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always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
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always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
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begin
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begin
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case (sel3)
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case (sel3) /* synopsys full_case parallel_case */
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`OC8051_AS3_DP: src3= dptr[15:8];
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`OC8051_AS3_DP: src3= dptr[15:8];
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`OC8051_AS3_PC: src3= pc[15:8];
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`OC8051_AS3_PC: src3= pc[15:8];
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default: src3= 16'h0;
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// default: src3= 16'h0;
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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