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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_comp.v] - Diff between revs 10 and 16
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_comp (sel, b_in, cy, acc, ram, op2, des, eq);
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module oc8051_comp (sel, b_in, cy, acc, des, eq);
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//
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//
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// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
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// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
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// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
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// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
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// cy (in) carry flag [oc8051_psw.data_out[7] ]
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// cy (in) carry flag [oc8051_psw.data_out[7] ]
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// acc (in) accumulator [oc8051_acc.data_out]
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// acc (in) accumulator [oc8051_acc.data_out]
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//
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//
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input [1:0] sel;
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input [1:0] sel;
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input b_in, cy;
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input b_in, cy;
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input [7:0] acc, ram, op2, des;
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input [7:0] acc, des;
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output eq;
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output eq;
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reg eq;
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reg eq;
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always @(sel or b_in or cy or acc or ram or op2 or des)
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always @(sel or b_in or cy or acc or des)
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begin
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begin
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case (sel)
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case (sel)
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`OC8051_CSS_AZ : eq = (acc == 8'h00);
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`OC8051_CSS_AZ : eq = (acc == 8'h00);
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`OC8051_CSS_DES : eq = (des == 8'h00);
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`OC8051_CSS_DES : eq = (des == 8'h00);
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`OC8051_CSS_CY : eq = cy;
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`OC8051_CSS_CY : eq = cy;
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