URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_cy_select.v] - Diff between revs 95 and 179

Rev 95	Rev 179
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2003/04/02 11:26:21 simont`
	`// updating...`
	`//`
`// Revision 1.2 2002/09/30 17:33:59 simont`	`// Revision 1.2 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
`//`	`//`
`//`	`//`

Line 70...	Line 73...
`output data_out;`	`output data_out;`
`reg data_out;`	`reg data_out;`

`always @(cy_sel or cy_in or data_in)`	`always @(cy_sel or cy_in or data_in)`
`begin`	`begin`
`case (cy_sel)`	`case (cy_sel) /* synopsys full_case parallel_case */`
`OC8051_CY_0: data_out = 1'b0;	`OC8051_CY_0: data_out = 1'b0;
`OC8051_CY_PSW: data_out = cy_in;	`OC8051_CY_PSW: data_out = cy_in;
`OC8051_CY_RAM: data_out = data_in;	`OC8051_CY_RAM: data_out = data_in;
`OC8051_CY_1: data_out = 1'b1;	`OC8051_CY_1: data_out = 1'b1;
`default: data_out = 1'bx;`
`endcase`	`endcase`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`