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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.18 2003/05/05 15:46:36 simont
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// add aditional alu destination to solve critical path.
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//
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// Revision 1.17 2003/04/25 17:15:51 simont
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// Revision 1.17 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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//
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//
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// Revision 1.16 2003/04/09 16:24:03 simont
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// Revision 1.16 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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Line 112... |
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input clk, rst, eq, mem_wait, wait_data;
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input clk, rst, eq, mem_wait, wait_data;
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input [7:0] op_in;
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input [7:0] op_in;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output [1:0] psw_set, cy_sel, wr_sfr_o, comp_sel;
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output [1:0] psw_set, cy_sel, wr_sfr_o, src_sel2, comp_sel;
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output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
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output [2:0] mem_act, src_sel1, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
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output [3:0] alu_op_o;
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output [3:0] alu_op_o;
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output rd;
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output rd;
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reg rmw;
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reg rmw;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg [1:0] comp_sel, psw_set, cy_sel, wr_sfr;
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reg [3:0] alu_op;
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reg [3:0] alu_op;
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reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel;
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reg [1:0] src_sel2, comp_sel, psw_set, cy_sel, wr_sfr;
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reg [2:0] mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel;
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//
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//
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// op instruction buffer
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// op instruction buffer
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reg [1:0] state;
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reg [1:0] state;
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