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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2003/06/03 17:09:57 simont
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// pipelined acces to axternal instruction interface added.
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//
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// Revision 1.20 2003/05/06 11:10:38 simont
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// Revision 1.20 2003/05/06 11:10:38 simont
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// optimize state machine.
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// optimize state machine.
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//
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//
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// Revision 1.19 2003/05/06 09:41:35 simont
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// Revision 1.19 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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| Line 163... |
Line 166... |
//
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//
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// main block
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// main block
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// unregisterd outputs
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// unregisterd outputs
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always @(op_cur or eq or state_dec or mem_wait)
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always @(op_cur or eq or state_dec or mem_wait)
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begin
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begin
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case (state_dec)
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case (state_dec) /* synopsys full_case parallel_case */
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2'b01: begin
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2'b01: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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ram_rd_sel = `OC8051_RRS_B;
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ram_rd_sel = `OC8051_RRS_B;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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ram_rd_sel = `OC8051_RRS_B;
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ram_rd_sel = `OC8051_RRS_B;
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| Line 184... |
Line 187... |
pc_sel = `OC8051_PIS_DC;
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pc_sel = `OC8051_PIS_DC;
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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rmw = `OC8051_RMW_N;
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rmw = `OC8051_RMW_N;
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end
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end
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2'b10: begin
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2'b10: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_SJMP : begin
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`OC8051_SJMP : begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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pc_wr = `OC8051_PCW_Y;
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pc_wr = `OC8051_PCW_Y;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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| Line 331... |
Line 334... |
endcase
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endcase
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rmw = `OC8051_RMW_N;
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rmw = `OC8051_RMW_N;
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stb_i = 1'b1;
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stb_i = 1'b1;
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end
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end
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2'b11: begin
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2'b11: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_CJNE_R : begin
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`OC8051_CJNE_R : begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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pc_wr = `OC8051_PCW_N;
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pc_wr = `OC8051_PCW_N;
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pc_sel = `OC8051_PIS_DC;
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pc_sel = `OC8051_PIS_DC;
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end
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end
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| Line 393... |
Line 396... |
comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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rmw = `OC8051_RMW_N;
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rmw = `OC8051_RMW_N;
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stb_i = 1'b1;
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stb_i = 1'b1;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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default: begin
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2'b00: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_ACALL :begin
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`OC8051_ACALL :begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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pc_wr = `OC8051_PCW_Y;
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pc_wr = `OC8051_PCW_Y;
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pc_sel = `OC8051_PIS_I11;
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pc_sel = `OC8051_PIS_I11;
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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| Line 1196... |
Line 1199... |
psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= #1 `OC8051_PS_NOT;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <= #1 `OC8051_WRS_N;
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end else if (!wait_data) begin
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end else if (!wait_data) begin
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case (state_dec)
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case (state_dec) /* synopsys parallel_case */
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2'b01: begin
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2'b01: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_MOVC_DP :begin
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`OC8051_MOVC_DP :begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= #1 `OC8051_ALU_NOP;
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| Line 1294... |
Line 1297... |
endcase
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endcase
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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end
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end
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2'b10: begin
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2'b10: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_ACALL :begin
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`OC8051_ACALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= #1 `OC8051_ALU_NOP;
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| Line 1350... |
Line 1353... |
src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <= #1 `OC8051_WRS_N;
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end
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end
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2'b11: begin
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2'b11: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_RET : begin
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`OC8051_RET : begin
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src_sel1 <= #1 `OC8051_AS1_RAM;
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src_sel1 <= #1 `OC8051_AS1_RAM;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= #1 `OC8051_ALU_NOP;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= #1 `OC8051_PS_NOT;
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| Line 1389... |
Line 1392... |
cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <= #1 `OC8051_WRS_N;
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end
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end
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default: begin
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default: begin
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_ACALL :begin
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`OC8051_ACALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCL;
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src_sel1 <= #1 `OC8051_AS1_PCL;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= #1 `OC8051_ALU_NOP;
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| Line 2635... |
Line 2638... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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state <= #1 2'b11;
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state <= #1 2'b11;
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else if (!mem_wait & !wait_data) begin
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else if (!mem_wait & !wait_data) begin
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case (state)
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case (state) /* synopsys parallel_case */
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2'b10: state <= #1 2'b01;
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2'b10: state <= #1 2'b01;
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2'b11: state <= #1 2'b10;
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2'b11: state <= #1 2'b10;
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2'b00:
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2'b00:
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casex (op_in)
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casex (op_in) /* synopsys full_case parallel_case */
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`OC8051_ACALL : state <= #1 2'b10;
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`OC8051_ACALL : state <= #1 2'b10;
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`OC8051_AJMP : state <= #1 2'b10;
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`OC8051_AJMP : state <= #1 2'b10;
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`OC8051_CJNE_R : state <= #1 2'b10;
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`OC8051_CJNE_R : state <= #1 2'b10;
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`OC8051_CJNE_I : state <= #1 2'b10;
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`OC8051_CJNE_I : state <= #1 2'b10;
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`OC8051_CJNE_D : state <= #1 2'b10;
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`OC8051_CJNE_D : state <= #1 2'b10;
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| Line 2669... |
Line 2672... |
`OC8051_JNB : state <= #1 2'b10;
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`OC8051_JNB : state <= #1 2'b10;
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`OC8051_JNZ : state <= #1 2'b10;
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`OC8051_JNZ : state <= #1 2'b10;
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`OC8051_JZ : state <= #1 2'b10;
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`OC8051_JZ : state <= #1 2'b10;
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`OC8051_DIV : state <= #1 2'b11;
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`OC8051_DIV : state <= #1 2'b11;
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`OC8051_MUL : state <= #1 2'b11;
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`OC8051_MUL : state <= #1 2'b11;
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default : state <= #1 2'b00;
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// default : state <= #1 2'b00;
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endcase
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endcase
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default: state <= #1 2'b00;
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default: state <= #1 2'b00;
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endcase
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endcase
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end
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end
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end
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end
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| Line 2686... |
Line 2689... |
if (rst) begin
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if (rst) begin
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mem_act <= #1 `OC8051_MAS_NO;
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mem_act <= #1 `OC8051_MAS_NO;
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end else if (!rd) begin
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end else if (!rd) begin
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mem_act <= #1 `OC8051_MAS_NO;
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mem_act <= #1 `OC8051_MAS_NO;
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end else
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end else
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casex (op_cur)
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
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`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
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`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
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`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
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`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
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`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
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`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
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`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
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`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
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`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
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