| Line 221... |
Line 221... |
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_N;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
|
`OC8051_DIV : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_DIV;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
|
`OC8051_MUL : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_MUL;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
default begin
|
default begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
| Line 583... |
Line 621... |
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_N;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
|
`OC8051_DIV : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_DIV;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
|
`OC8051_MUL : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_MUL;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
default begin
|
default begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
| Line 758... |
Line 834... |
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_N;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
|
`OC8051_DIV : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_DIV;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
|
`OC8051_MUL : begin
|
|
ram_rd_sel = `OC8051_RRS_D;
|
|
ram_wr_sel = `OC8051_RWS_B;
|
|
src_sel1 = `OC8051_ASS_ACC;
|
|
src_sel2 = `OC8051_ASS_RAM;
|
|
alu_op = `OC8051_ALU_MUL;
|
|
wr = 1'b1;
|
|
psw_set = `OC8051_PS_OV;
|
|
cy_sel = `OC8051_CY_0;
|
|
pc_wr = `OC8051_PCW_N;
|
|
pc_sel = `OC8051_PIS_DC;
|
|
imm_sel = `OC8051_IDS_DC;
|
|
src_sel3 = `OC8051_AS3_DC;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
|
wad2 = `OC8051_WAD_Y;
|
|
rom_addr_sel = `OC8051_RAS_PC;
|
|
ext_addr_sel = `OC8051_EAS_DC;
|
|
end
|
default begin
|
default begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
ram_wr_sel = `OC8051_RWS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel1 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
src_sel2 = `OC8051_ASS_DC;
|
| Line 818... |
Line 932... |
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_N;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
|
|
|
|
`OC8051_ADD_R : begin
|
`OC8051_ADD_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_wr_sel = `OC8051_RWS_ACC;
|
ram_wr_sel = `OC8051_RWS_ACC;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel2 = `OC8051_ASS_RAM;
|
src_sel2 = `OC8051_ASS_RAM;
|
| Line 1876... |
Line 1988... |
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_wr_sel = `OC8051_RWS_B;
|
ram_wr_sel = `OC8051_RWS_B;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel2 = `OC8051_ASS_RAM;
|
src_sel2 = `OC8051_ASS_RAM;
|
alu_op = `OC8051_ALU_DIV;
|
alu_op = `OC8051_ALU_DIV;
|
wr = 1'b1;
|
wr = 1'b0;
|
psw_set = `OC8051_PS_OV;
|
psw_set = `OC8051_PS_OV;
|
cy_sel = `OC8051_CY_0;
|
cy_sel = `OC8051_CY_0;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
imm_sel = `OC8051_IDS_DC;
|
imm_sel = `OC8051_IDS_DC;
|
src_sel3 = `OC8051_AS3_DC;
|
src_sel3 = `OC8051_AS3_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_Y;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
| Line 2390... |
Line 2502... |
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_wr_sel = `OC8051_RWS_B;
|
ram_wr_sel = `OC8051_RWS_B;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel1 = `OC8051_ASS_ACC;
|
src_sel2 = `OC8051_ASS_RAM;
|
src_sel2 = `OC8051_ASS_RAM;
|
alu_op = `OC8051_ALU_MUL;
|
alu_op = `OC8051_ALU_MUL;
|
wr = 1'b1;
|
wr = 1'b0;
|
psw_set = `OC8051_PS_OV;
|
psw_set = `OC8051_PS_OV;
|
cy_sel = `OC8051_CY_0;
|
cy_sel = `OC8051_CY_0;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
imm_sel = `OC8051_IDS_DC;
|
imm_sel = `OC8051_IDS_DC;
|
src_sel3 = `OC8051_AS3_DC;
|
src_sel3 = `OC8051_AS3_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
rmw = `OC8051_RMW_N; bit_addr = 1'b0;
|
wad2 = `OC8051_WAD_Y;
|
wad2 = `OC8051_WAD_N;
|
rom_addr_sel = `OC8051_RAS_PC;
|
rom_addr_sel = `OC8051_RAS_PC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
ext_addr_sel = `OC8051_EAS_DC;
|
end
|
end
|
`OC8051_ORL_D : begin
|
`OC8051_ORL_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
| Line 2944... |
Line 3056... |
`OC8051_JMP : state <= #1 2'b10;
|
`OC8051_JMP : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JZ : state <= #1 2'b10;
|
`OC8051_JZ : state <= #1 2'b10;
|
|
`OC8051_DIV : state <= #1 2'b11;
|
|
`OC8051_MUL : state <= #1 2'b11;
|
default: state <= #1 2'b00;
|
default: state <= #1 2'b00;
|
endcase
|
endcase
|
default: state <= #1 2'b00;
|
default: state <= #1 2'b00;
|
endcase
|
endcase
|
end
|
end
|
