OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Diff between revs 20 and 23

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 20 Rev 23
Line 627... Line 627...
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_DIV;
          alu_op = `OC8051_ALU_DIV;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
          ext_addr_sel = `OC8051_EAS_DC;
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_MUL;
          alu_op = `OC8051_ALU_MUL;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
          ext_addr_sel = `OC8051_EAS_DC;
        end
        end
      default begin
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;
Line 840... Line 840...
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_DIV;
          alu_op = `OC8051_ALU_DIV;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
          ext_addr_sel = `OC8051_EAS_DC;
        end
        end
      `OC8051_MUL : begin
      `OC8051_MUL : begin
          ram_rd_sel = `OC8051_RRS_D;
          ram_rd_sel = `OC8051_RRS_D;
          ram_wr_sel = `OC8051_RWS_B;
          ram_wr_sel = `OC8051_RWS_B;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel1 = `OC8051_ASS_ACC;
          src_sel2 = `OC8051_ASS_RAM;
          src_sel2 = `OC8051_ASS_RAM;
          alu_op = `OC8051_ALU_MUL;
          alu_op = `OC8051_ALU_MUL;
          wr = 1'b1;
          wr = 1'b0;
          psw_set = `OC8051_PS_OV;
          psw_set = `OC8051_PS_OV;
          cy_sel = `OC8051_CY_0;
          cy_sel = `OC8051_CY_0;
          pc_wr = `OC8051_PCW_N;
          pc_wr = `OC8051_PCW_N;
          pc_sel = `OC8051_PIS_DC;
          pc_sel = `OC8051_PIS_DC;
          imm_sel = `OC8051_IDS_DC;
          imm_sel = `OC8051_IDS_DC;
          src_sel3 = `OC8051_AS3_DC;
          src_sel3 = `OC8051_AS3_DC;
          comp_sel = `OC8051_CSS_DC;
          comp_sel = `OC8051_CSS_DC;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
          wad2 = `OC8051_WAD_Y;
          wad2 = `OC8051_WAD_N;
          rom_addr_sel = `OC8051_RAS_PC;
          rom_addr_sel = `OC8051_RAS_PC;
          ext_addr_sel = `OC8051_EAS_DC;
          ext_addr_sel = `OC8051_EAS_DC;
        end
        end
      default begin
      default begin
          ram_rd_sel = `OC8051_RRS_DC;
          ram_rd_sel = `OC8051_RRS_DC;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.