URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Diff between revs 114 and 118

Rev 114	Rev 118
Line 337...	Line 337...


`//`	`//`
`//write sfr`	`//write sfr`
`//`	`//`
`define OC8051_WRS_N 3'b000 //no	`define OC8051_WRS_N 2'b00 //no
`define OC8051_WRS_ACC1 3'b001 // acc destination 1	`define OC8051_WRS_ACC1 2'b01 // acc destination 1
`define OC8051_WRS_ACC2 3'b010 // acc destination 2	`define OC8051_WRS_ACC2 2'b10 // acc destination 2
`define OC8051_WRS_DPTR 3'b011 // data pointer	`define OC8051_WRS_DPTR 2'b11 // data pointer
`define OC8051_WRS_BA 3'b100 // a, b register


`//`	`//`
`// ram read select`	`// ram read select`
`//`	`//`
Line 368...	Line 367...
`define OC8051_RWS_D 3'b001 // direct addressing	`define OC8051_RWS_D 3'b001 // direct addressing
`define OC8051_RWS_I 3'b010 // indirect addressing	`define OC8051_RWS_I 3'b010 // indirect addressing
`define OC8051_RWS_SP 3'b011 // stack pointer	`define OC8051_RWS_SP 3'b011 // stack pointer
`define OC8051_RWS_D3 3'b101 // direct address (op3)	`define OC8051_RWS_D3 3'b101 // direct address (op3)
`define OC8051_RWS_D1 3'b110 // direct address (op1)	`define OC8051_RWS_D1 3'b110 // direct address (op1)
	`define OC8051_RWS_B 3'b111 // b register
`define OC8051_RWS_DC 3'b000 //	`define OC8051_RWS_DC 3'b000 //

`//`	`//`
`// pc in select`	`// pc in select`
`//`	`//`