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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/04/02 11:22:15 simont
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// fix bug.
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//
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// Revision 1.4 2003/01/21 14:08:18 simont
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// Revision 1.4 2003/01/21 14:08:18 simont
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// fix bugs
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// fix bugs
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//
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//
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// Revision 1.3 2003/01/13 14:14:41 simont
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// Revision 1.3 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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| Line 112... |
Line 115... |
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
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reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
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// valid[x]=1 if block x is valid;
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// valid[x]=1 if block x is valid;
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reg [BL_NUM:0] valid;
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reg [BL_NUM:0] valid;
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// con0, con2 contain temporal control information of current address and corrent address+2
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// con0, con2 contain temporal control information of current address and corrent address+2
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// part of con_buf memory
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// part of con_buf memory
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reg [14-ADR_WIDTH:0] con0, con2;
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reg [13-ADR_WIDTH:0] con0, con2;
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//current upper address,
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//current upper address,
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reg [13-ADR_WIDTH:0] cadr0, cadr2;
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reg [13-ADR_WIDTH:0] cadr0, cadr2;
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reg stb_b;
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reg stb_b;
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// byte_select in 32 bit line (adr_i[1:0])
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// byte_select in 32 bit line (adr_i[1:0])
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reg [1:0] byte_sel;
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reg [1:0] byte_sel;
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| Line 126... |
Line 129... |
reg [31:0] data1_i;
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reg [31:0] data1_i;
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// temporaly data from ram
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// temporaly data from ram
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reg [15:0] tmp_data1;
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reg [15:0] tmp_data1;
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reg wr1, wr1_t, stb_it;
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reg wr1, wr1_t, stb_it;
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////////////////
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reg vaild_h, vaild_l;
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wire [31:0] data0, data1_o;
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wire [31:0] data0, data1_o;
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wire cy, cy1;
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wire cy, cy1;
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wire [BL_WIDTH-1:0] adr_i2;
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wire [BL_WIDTH-1:0] adr_i2;
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wire hit, hit_l, hit_h;
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wire hit, hit_l, hit_h;
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wire [ADR_WIDTH-1:0] adr_r, addr1;
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wire [ADR_WIDTH-1:0] adr_r, addr1;
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| Line 139... |
Line 147... |
wire [LINE_WIDTH-1:0] adr_r1;
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wire [LINE_WIDTH-1:0] adr_r1;
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assign cy = &adr_i[LINE_WIDTH+1:1];
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assign cy = &adr_i[LINE_WIDTH+1:1];
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assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
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assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
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assign hit_l =(con0=={cadr0,1'b1});
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assign hit_l = (con0==cadr0) & vaild_l;
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assign hit_h =(con2=={cadr2,1'b1});
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assign hit_h = (con2==cadr2) & vaild_h;
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assign hit = hit_l && hit_h;
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assign hit = hit_l && hit_h;
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assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
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assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
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assign addr1 = wr1 ? adr_w : adr_r;
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assign addr1 = wr1 ? adr_w : adr_r;
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assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
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assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
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//assign ack_o = hit;
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assign ack_o = hit && stb_it;
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assign ack_o = hit && stb_it;
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
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assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.wr1(wr1));
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.wr1(wr1));
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defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
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defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
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defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
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defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
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/*
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generic_dpram #(ADR_WIDTH, 32) oc8051_cache_ram1(
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.rclk ( clk ),
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( adr_i[ADR_WIDTH+1:2] ),
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.do ( data0 ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr1 ),
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.waddr ( addr1 ),
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.di ( data1_i )
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);
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*/
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always @(stb_b or data0 or data1 or byte_sel)
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always @(stb_b or data0 or data1 or byte_sel)
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begin
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begin
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if (stb_b) begin
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if (stb_b) begin
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case (byte_sel)
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case (byte_sel)
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2'b00 : dat_o = data0;
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2'b00 : dat_o = data0;
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| Line 181... |
Line 212... |
begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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con0 <= #1 9'h0;
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con0 <= #1 9'h0;
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con2 <= #1 9'h0;
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con2 <= #1 9'h0;
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vaild_h <= #1 1'b0;
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vaild_l <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
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con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
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con2 <= #1 {con_buf[adr_i2], valid[adr_i2]};
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con2 <= #1 {con_buf[adr_i2]};
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vaild_l <= #1 valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]];
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vaild_h <= #1 valid[adr_i2];
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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| Line 242... |
Line 277... |
if (&cyc)
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if (&cyc)
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begin
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begin
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cyc <= #1 2'b00;
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cyc <= #1 2'b00;
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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// con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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cyc <= #1 cyc + 1'b1;
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cyc <= #1 cyc + 1'b1;
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cyc_o <= #1 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b0;
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end
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end
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/* case (cyc)
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2'b00: begin
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cyc <= #1 2'b01;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b01: begin
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cyc <= #1 2'b10;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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2'b10: begin
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cyc <= #1 2'b11;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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default: begin
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cyc <= #1 2'b00;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
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valid[mis_adr[7:4]] <= #1 1'b1;
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end
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endcase*/
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end
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end
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else
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else
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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end
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end
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