URL
https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_icache.v] - Diff between revs 174 and 179
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 174 |
Rev 179 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2003/06/20 13:36:37 simont
|
|
// ram modules added.
|
|
//
|
// Revision 1.7 2003/05/05 10:35:35 simont
|
// Revision 1.7 2003/05/05 10:35:35 simont
|
// change to fit xrom.
|
// change to fit xrom.
|
//
|
//
|
// Revision 1.6 2003/04/03 19:15:37 simont
|
// Revision 1.6 2003/04/03 19:15:37 simont
|
// fix some bugs, use oc8051_cache_ram.
|
// fix some bugs, use oc8051_cache_ram.
|
| Line 215... |
Line 218... |
|
|
|
|
always @(stb_b or data0 or data1 or byte_sel)
|
always @(stb_b or data0 or data1 or byte_sel)
|
begin
|
begin
|
if (stb_b) begin
|
if (stb_b) begin
|
case (byte_sel)
|
case (byte_sel) /* synopsys full_case parallel_case */
|
2'b00 : dat_o = data0;
|
2'b00 : dat_o = data0;
|
2'b01 : dat_o = {data1[7:0], data0[31:8]};
|
2'b01 : dat_o = {data1[7:0], data0[31:8]};
|
2'b10 : dat_o = {data1[15:0], data0[31:16]};
|
2'b10 : dat_o = {data1[15:0], data0[31:16]};
|
default: dat_o = {8'h00, data1, data0[31:24]};
|
2'b11 : dat_o = {8'h00, data1, data0[31:24]};
|
endcase
|
endcase
|
end else begin
|
end else begin
|
dat_o = 32'h0;
|
dat_o = 32'h0;
|
end
|
end
|
end
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.