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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_indi_addr.v] - Diff between revs 2 and 4

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Rev 2 Rev 4
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  else
  else
    data_out = buff[{bank, sel}];
    data_out = buff[{bank, sel}];
end
end
 
 
endmodule
endmodule
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