URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Diff between revs 81 and 118

Rev 81	Rev 118
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2003/01/13 14:13:12 simont`
	`// initial import`
	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "oc8051_timescale.v"	`include "oc8051_timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
Line 267...	Line 270...
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};	`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
`OC8051_RWS_I : wr_addr = ri_r;	`OC8051_RWS_I : wr_addr = ri_r;
`OC8051_RWS_D : wr_addr = imm_r;	`OC8051_RWS_D : wr_addr = imm_r;
`OC8051_RWS_SP : wr_addr = sp_w;	`OC8051_RWS_SP : wr_addr = sp_w;
`OC8051_RWS_D3 : wr_addr = imm2_r;	`OC8051_RWS_D3 : wr_addr = imm2_r;
	`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
`default : wr_addr = 2'bxx;`	`default : wr_addr = 2'bxx;`
`endcase`	`endcase`
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`