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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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//
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// Revision 1.4 2003/04/16 10:04:09 simont
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// Revision 1.4 2003/04/16 10:04:09 simont
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// chance idat_ir to 24 bit wide
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// chance idat_ir to 24 bit wide
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//
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//
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// Revision 1.3 2003/04/11 10:05:08 simont
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// Revision 1.3 2003/04/11 10:05:08 simont
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// Change pc add value from 23'h to 16'h
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// Change pc add value from 23'h to 16'h
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| Line 87... |
Line 90... |
dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
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dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
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//interrupt interface
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//interrupt interface
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intr, int_v, int_ack,
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intr, int_v, int_ack,
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//alu
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//alu
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des1, des2,
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des_acc, des1, des2,
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//sfr's
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//sfr's
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dptr, ri, rn_mem, sp, sp_w, rn, acc, reti);
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dptr, ri, sp, sp_w, rn, acc, reti);
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input bit_in, sfr_bit, dack_i;
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input bit_in, sfr_bit, dack_i;
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input [2:0] mem_act;
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input [2:0] mem_act;
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input [7:0] in_ram, sfr, acc, sp_w;
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input [7:0] in_ram, sfr, acc, sp_w;
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input [31:0] idat_i;
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input [31:0] idat_i;
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| Line 102... |
Line 105... |
output bit_out, mem_wait, reti;
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output bit_out, mem_wait, reti;
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output [7:0] iram_out, wr_dat;
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output [7:0] iram_out, wr_dat;
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reg bit_out, reti;
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reg bit_out, reti;
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reg [7:0] iram_out, sp_r;
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reg [7:0] iram_out, sp_r;
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reg [2:0] rd_addr_r;
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reg rd_addr_r;
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input clk, rst, wr_i, wr_bit_i;
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input clk, rst, wr_i, wr_bit_i;
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output wr_o, wr_bit_o;
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output wr_o, wr_bit_o;
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//????
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//????
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reg dack_ir;
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reg dack_ir;
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| Line 117... |
Line 120... |
//
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//
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// rom_addr_sel
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// rom_addr_sel
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//
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//
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/////////////////////////////
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/////////////////////////////
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input iack_i;
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input iack_i;
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input [7:0] des1, des2;
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input [7:0] des_acc, des1, des2;
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output [15:0] iadr_o;
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output [15:0] iadr_o;
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wire ea_rom_sel;
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wire ea_rom_sel;
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/////////////////////////////
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/////////////////////////////
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//
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//
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// ext_addr_sel
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// ext_addr_sel
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//
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//
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/////////////////////////////
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/////////////////////////////
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input [7:0] ri, rn_mem, ddat_i;
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input [7:0] ri, ddat_i;
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input [15:0] dptr;
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input [15:0] dptr;
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output dstb_o, dwe_o;
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output dstb_o, dwe_o;
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output [7:0] ddat_o;
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output [7:0] ddat_o;
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output [15:0] dadr_o;
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output [15:0] dadr_o;
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| Line 214... |
Line 217... |
wire [7:0] isr_call;
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wire [7:0] isr_call;
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assign bank = rn[4:3];
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assign bank = rn[4:3];
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assign imm = op2_out;
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assign imm = op2_out;
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assign imm2 = op3_out;
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assign imm2 = op3_out;
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assign alu = {des2,des1};
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assign alu = {des2, des_acc};
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assign ea_rom_sel = ea && ea_int;
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assign ea_rom_sel = ea && ea_int;
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assign wr_o = wr_i;
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assign wr_o = wr_i;
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assign wr_bit_o = wr_bit_i;
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assign wr_bit_o = wr_bit_i;
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assign mem_wait = dmem_wait || imem_wait;
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assign mem_wait = dmem_wait || imem_wait;
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| Line 232... |
Line 235... |
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/////////////////////////////
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/////////////////////////////
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//
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//
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// ram_select
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// ram_select
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//
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//
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/////////////////////////////
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///////////////////////////// ??????????????????????
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always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)
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always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
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begin
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begin
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if (rd_addr_r[2] && !rd_ind) begin
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if (rd_addr_r && !rd_ind) begin
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iram_out = sfr;
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iram_out = sfr;
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bit_out = sfr_bit;
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bit_out = sfr_bit;
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end else if (~|rd_addr_r[2:0]) begin
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iram_out = rn_mem;
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bit_out = bit_in;
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end else begin
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end else begin
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iram_out = in_ram;
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iram_out = in_ram;
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bit_out = bit_in;
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bit_out = bit_in;
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end
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end
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end
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end
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| Line 310... |
Line 310... |
/////////////////////////////
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/////////////////////////////
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//
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//
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// output address is alu destination
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// output address is alu destination
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// (instructions MOVC)
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// (instructions MOVC)
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assign iadr_ot = istb_t ? iadr_t : pc;
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assign iadr_ot = (istb_t & !iack_i) ? iadr_t : pc;
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assign iadr_o = iadr_ot;
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assign iadr_o = iadr_ot;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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| Line 330... |
Line 330... |
end else if (ea_rom_sel && imem_wait) begin
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end else if (ea_rom_sel && imem_wait) begin
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imem_wait <= #1 1'b0;
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imem_wait <= #1 1'b0;
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end else if (ea_rom_sel && !imem_wait && istb_t) begin
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end else if (ea_rom_sel && !imem_wait && istb_t) begin
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istb_t <= #1 1'b0;
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istb_t <= #1 1'b0;
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end else if (mem_act==`OC8051_MAS_CODE) begin
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end else if (mem_act==`OC8051_MAS_CODE) begin
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iadr_t <= #1 {des2, des1};
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iadr_t <= #1 alu;
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istb_t <= #1 1'b1;
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istb_t <= #1 1'b1;
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imem_wait <= #1 1'b1;
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imem_wait <= #1 1'b1;
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end
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end
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end
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end
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| Line 495... |
Line 495... |
//
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//
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// pc
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// pc
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//
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//
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/////////////////////////////
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/////////////////////////////
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always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)
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always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
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begin
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begin
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if (int_buff || int_buff1) begin
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if (int_buff || int_buff1) begin
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//
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//
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//in case of interrupt hold valut, to be written to stack
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//in case of interrupt hold valut, to be written to stack
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pc= pc_buf;
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pc= pc_buf;
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| Line 653... |
Line 653... |
if (rst) begin
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if (rst) begin
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rn_r <= #1 5'd0;
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rn_r <= #1 5'd0;
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ri_r <= #1 8'h00;
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ri_r <= #1 8'h00;
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imm_r <= #1 8'h00;
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imm_r <= #1 8'h00;
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imm2_r <= #1 8'h00;
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imm2_r <= #1 8'h00;
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rd_addr_r <= #1 3'h0;
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rd_addr_r <= #1 1'b0;
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op1_r <= #1 8'h0;
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op1_r <= #1 8'h0;
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dack_ir <= #1 1'b0;
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dack_ir <= #1 1'b0;
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sp_r <= #1 1'b0;
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sp_r <= #1 1'b0;
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end else begin
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end else begin
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rn_r <= #1 rn;
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rn_r <= #1 rn;
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ri_r <= #1 ri;
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ri_r <= #1 ri;
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imm_r <= #1 imm;
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imm_r <= #1 imm;
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imm2_r <= #1 imm2;
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imm2_r <= #1 imm2;
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rd_addr_r <= #1 rd_addr[7:5];
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rd_addr_r <= #1 rd_addr[7];
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op1_r <= #1 op1_out;
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op1_r <= #1 op1_out;
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dack_ir <= #1 dack_i;
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dack_ir <= #1 dack_i;
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sp_r <= #1 sp;
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sp_r <= #1 sp;
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end
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end
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