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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 4 and 5
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| Rev 4 |
Rev 5 |
| Line 133... |
Line 133... |
end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) bit_out <= #1 8'h0;
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if (rst) bit_out <= #1 1'b0;
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else bit_out <= #1 data_out[rd_addr];
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else bit_out <= #1 data_out[rd_addr];
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end
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end
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endmodule
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endmodule
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