Subversion Repositories 8051

output [7:0] data_out;

output [7:0] data_out;

output [7:0] data_out_r;

output [7:0] data_out_r;

reg bit_out;

reg bit_out;

reg [7:0] data;

reg [7:0] data;

wire wr_psw;

wire wr_psw;

assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);

assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);

assign data_out = wr_psw ? {data_in[7:1],p}:{data[7:1], p};

assign data_out = wr_psw ? {data_in[7:1],p}:{data[7:1], p};

//

//

//case writing to psw

//case writing to psw

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

begin

begin

  if (rst)

  if (rst)

    data <= #1 `OC8051_RST_PSW;

    data <= #1 `OC8051_RST_PSW;

//

//

// write to psw (byte addressable)

// write to psw (byte addressable)

//

//

// write to psw (bit addressable)

// write to psw (bit addressable)

  else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))

  else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))

    data[wr_addr[2:0]] <= #1 cy_in;

    data[wr_addr[2:0]] <= #1 cy_in;

  else begin

  else begin

//

//

//write carry, overflov and ac

//write carry, overflov and ac

        data[7] <= #1 cy_in;

        data[7] <= #1 cy_in;

        data[6] <= #1 ac_in;

        data[6] <= #1 ac_in;

        data[2] <= #1 ov_in;

        data[2] <= #1 ov_in;

      end

      end

    endcase

    endcase

  end

  end

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

begin

begin

  if (rst) bit_out <= #1 1'b0;

  if (rst) bit_out <= #1 1'b0;