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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ram_top.v] - Diff between revs 172 and 174
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| Rev 172 |
Rev 174 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/06/17 14:17:22 simont
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// BIST signals added.
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//
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// Revision 1.8 2003/04/02 16:12:04 simont
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// Revision 1.8 2003/04/02 16:12:04 simont
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// generic_dpram used
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// generic_dpram used
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//
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//
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// Revision 1.7 2003/04/02 11:26:21 simont
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// Revision 1.7 2003/04/02 11:26:21 simont
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// updating...
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// updating...
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| Line 129... |
Line 132... |
reg [2:0] bit_select;
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reg [2:0] bit_select;
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assign bit_data_out = rd_data[bit_select];
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assign bit_data_out = rd_data[bit_select];
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generic_dpram #(ram_aw, 8) oc8051_ram1(
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.rclk ( clk ),
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( rd_addr_m ),
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.do ( rd_data ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr ),
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.waddr ( wr_addr_m ),
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.di ( wr_data_m )
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);
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oc8051_ram_256x8_two_bist oc8051_idata(
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.clk ( clk ),
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.rst ( rst ),
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.rd_addr ( rd_addr_m ),
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.rd_data ( rd_data ),
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.rd_en ( 1'b1 ),
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.wr_addr ( wr_addr_m ),
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.wr_data ( wr_data_m ),
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.wr_en ( 1'b1 ),
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.wr ( wr )
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`ifdef OC8051_BIST
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,
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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`endif
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);
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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bit_addr_r <= #1 1'b0;
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bit_addr_r <= #1 1'b0;
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bit_select <= #1 3'b0;
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bit_select <= #1 3'b0;
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