URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_rom.v] - Diff between revs 149 and 179

Rev 149	Rev 179
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2003/06/03 17:09:57 simont`
	`// pipelined acces to axternal instruction interface added.`
	`//`
`// Revision 1.2 2003/04/03 19:17:19 simont`	`// Revision 1.2 2003/04/03 19:17:19 simont`
// add `include "oc8051_defines.v"	// add `include "oc8051_defines.v"
`//`	`//`
`// Revision 1.1 2003/04/02 11:16:22 simont`	`// Revision 1.1 2003/04/02 11:16:22 simont`
`// initial inport`	`// initial inport`
Line 228...	Line 231...

`//`	`//`
`// always read tree bits in row`	`// always read tree bits in row`
`always @(posedge clk)`	`always @(posedge clk)`
`begin`	`begin`
`case(addr[6:0])`	`case(addr[6:0]) /* synopsys parallel_case */`
`7'd0: begin`	`7'd0: begin`
`data1 <= #1 int_data0;`	`data1 <= #1 int_data0;`
`data2 <= #1 int_data1;`	`data2 <= #1 int_data1;`
`data3 <= #1 int_data2;`	`data3 <= #1 int_data2;`
`end`	`end`