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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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//
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// Revision 1.9 2003/04/09 16:24:03 simont
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// Revision 1.9 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.8 2003/04/09 15:49:42 simont
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// Revision 1.8 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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| Line 90... |
Line 93... |
sp, sp_w,
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sp, sp_w,
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bank_sel,
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bank_sel,
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desAc, desOv,
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desAc, desOv,
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srcAc, cy,
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srcAc, cy,
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psw_set, rmw,
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psw_set, rmw,
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comp_sel,
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comp_wait,
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_out,
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p0_out,
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| Line 150... |
Line 155... |
int0,
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int0,
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int1,
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int1,
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reti,
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reti,
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wr_bit;
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wr_bit;
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input [1:0] psw_set,
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input [1:0] psw_set,
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wr_sfr;
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wr_sfr,
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comp_sel;
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input [2:0] ram_rd_sel,
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input [2:0] ram_rd_sel,
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ram_wr_sel;
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ram_wr_sel;
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input [7:0] adr0, //address 0 input
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input [7:0] adr0, //address 0 input
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adr1, //address 1 input
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adr1, //address 1 input
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dat1, //data 1 input (des1)
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dat1, //data 1 input (des1)
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| Line 162... |
Line 168... |
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output bit_out,
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output bit_out,
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intr,
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intr,
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srcAc,
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srcAc,
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cy,
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cy,
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wait_data;
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wait_data,
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comp_wait;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] dat0, //data output
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output [7:0] dat0, //data output
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int_src,
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int_src,
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dptr_hi,
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dptr_hi,
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dptr_lo,
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dptr_lo,
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| Line 524... |
Line 531... |
adr0_r <= #1 adr0;
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adr0_r <= #1 adr0;
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ram_wr_sel_r <= #1 ram_wr_sel;
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ram_wr_sel_r <= #1 ram_wr_sel;
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wr_bit_r <= #1 wr_bit;
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wr_bit_r <= #1 wr_bit;
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end
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end
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assign comp_wait = !(
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((comp_sel==`OC8051_CSS_AZ) &
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((wr_sfr==`OC8051_WRS_ACC1) |
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(wr_sfr==`OC8051_WRS_ACC2) |
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((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
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((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
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((comp_sel==`OC8051_CSS_CY) &
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((|psw_set) |
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((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
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((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
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((comp_sel==`OC8051_CSS_BIT) &
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((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
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((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
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//
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//
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//set output in case of address (byte)
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//set output in case of address (byte)
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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| Line 541... |
Line 563... |
(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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end else if (
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end else if ((
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(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
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((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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) & !wait_data) begin
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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end else begin
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end else begin
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